G01R31/2656

Terahertz Plasmonics for Testing Very Large-Scale Integrated Circuits under Bias

Various embodiments are described that relate to failure determination for an integrated circuit. An integrated circuit can be tested to determine if the integrated circuit is functioning properly. The integrated circuit can be subjected to a specific radiation such that the integrated circuit produces a response. This response can be compared against an expected response to determine if the response matches the expected response. If the response does not match the expected response, then the integrated circuit fails the test. If the response matches the expected response, then the integrated circuit passes the test.

Integrated circuit with optical tunnel

The invention relates to an integrated circuit with an active transistor area and a plurality of wiring layers arranged above the active transistor area. At least one optical device is integrated in the active transistor area. The optical device is electrically connected with at least one of the wiring layers. At least one optical tunnel extends from the at least one optical device through the plurality of wiring layers to a surface of an uppermost wiring layer of the plurality of wiring layers facing away from the active transistor area.

OPTICAL MEASUREMENT DEVICE
20210333207 · 2021-10-28 · ·

An embodiment includes a light source that generates measurement light including a first wavelength, a light source that generates stimulation light including a second wavelength, an optical coupling unit that is a WDM optical coupler including optical fibers branched between an output end and input ends, the input ends being optically coupled to an output of the light sources, and the WDM optical coupler combining the measurement light with the stimulation light and outputting the combination light from the output end, a photodetector that detects an intensity of reflected light from a DUT, a light irradiation and guide system that guides the combination light toward a measurement point on the DUT and guides the reflected light from the measurement point toward the photodetector, and a galvanometer mirror that moves the measurement point, and the optical fibers propagate light in a single mode for the first wavelength.

Method for inspecting semiconductor device

Provided is a method for inspecting a semiconductor device which performs an inspection of a semiconductor device as an object to be inspected, including attaching an adhesive tape to a surface to be inspected of the semiconductor device, acquiring a first pattern image based on a light detected from a region including a surface of the surface to be inspected to which the adhesive tape is attached, inputting an electrical signal to the semiconductor device to which the adhesive tape is attached, acquiring a first heat generation image by detecting light according to heat radiation from the region including the surface to which the adhesive tape is attached in a state in which the electrical signal is input, and superimposing the first pattern image and the first heat generation image.

SEMICONDUCTOR SAMPLE INSPECTION DEVICE AND INSPECTION METHOD

An inspection device includes a reference signal output section, a noise removal section, and an electrical characteristic measurement section. The reference signal output section is connected to an external power supply device in electrical parallel with a semiconductor sample, and outputs a reference signal according to the output of the external power supply device. The noise removal section outputs a noise removal signal obtained by removing a noise component of the output of the external power supply device from the current signal output from the semiconductor sample based on the reference signal. The electrical characteristic measurement section measures the electrical characteristic of the semiconductor sample based on the noise removal signal. The inspection device measures the electrical characteristic of the semiconductor sample to which a voltage is being applied by the external power supply device and which is being irradiated and scanned with light. The inspection device outputs a defective portion of the semiconductor sample based on the electrical characteristic.

Pump and probe type second harmonic generation metrology

Various approaches to can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation and in some cases may utilize pump and probe radiation. Other approaches involve determining current flow from a sample illuminated with radiation.

Metrology apparatus and method for determining a characteristic of one or more structures on a substrate

Disclosed is a method for obtaining a computationally determined interference electric field describing scattering of radiation by a pair of structures comprising a first structure and a second structure on a substrate. The method comprises determining a first electric field relating to first radiation scattered by the first structure; determining a second electric field relating to second radiation scattered by the second structure; and computationally determining the interference of the first electric field and second electric field, to obtain a computationally determined interference electric field.

DUAL-SIDED WAFER IMAGING APPARATUS AND METHODS THEREOF
20210223308 · 2021-07-22 ·

The present disclosure provides a dual-sided wafer imaging apparatus and methods thereof. The dual-sided wafer imaging apparatus includes one or more load ports, one or more mechanical arms for transporting a wafer, a wafer transfer stage, a first line scan camera mounted below the wafer transfer stage, a second line scan camera mounted above the wafer transfer stage, a first optical lens mounted on the first line scan camera, a second optical lens mounted on the second line scan camera, and line light sources respectively mounted below and above the wafer transfer stage. The load ports are configured for an automated load operation or unload operation of a wafer pod of an automated transport equipment. The wafer transfer stage includes vacuum suction points in contact with a backside of the wafer, and the wafer transfer stage further includes a drive motor producing a linear reciprocating motion for moving the wafer.

DEVICE AND METHOD FOR MONITORING POWER SEMICONDUCTOR DIE

A device comprising at least one power semiconductor die coated with a metallization and at least one light guide having two opposite ends. The first end is able to be connected at least to a light source and to a light receiver. The second end is permanently fixed facing to a surface of the metallization such that to form a light path towards said surface and a light path from said surface.

METHOD OF ANALYZING SEMICONDUCTOR STRUCTURE
20210172995 · 2021-06-10 ·

A method includes providing a detector disposed above a semiconductor structure; identifying a portion of the semiconductor structure at a temperature substantially greater than a predetermined threshold by the detector; rotating the stage; and deriving a position of the portion of the semiconductor structure based upon the rotation of the stage.