The present application discloses a method and apparatus for calculating the kink current of SOI device, which is used to solve the problem that the kink current calculation in the prior art is not accurate and is not suitable for circuit simulation. The method includes: obtaining the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current of the SOI device respectively; and calculating the kink current of the SOI device according to the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current.

According to one embodiment, an electronic circuit includes: a current supply circuit, a detection circuit, a timing generation circuit, a sample hold circuit and a calculation circuit. The current supply circuit supplies a sine wave current for measurement to a gate terminal of a semiconductor switching device. The detection circuit detects a sine wave voltage generated in response to supply of the sine wave current to generate a detection signal. The timing generation circuit counts cycles of the sine wave voltage. The sample hold circuit samples the detection signal at a timing depending on a count value of the timing generation circuit. The calculation circuit calculates a gate resistance of the semiconductor switching device based on the sampled voltage.

A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.

Laser-assisted integrated circuit (IC) device testing apparatus capable of inducing hot carrier injection (HCI) within selected transistors of an IC device. A laser source of sufficiently high output power (e.g., 1W) and short pulse duration (e.g., 100 fs) can generate enough hot carriers through a multi-photon (e.g., TPA) carrier injection mechanism to significantly accelerate HCI aging even at low transistor voltage bias (e.g., <1.5V). Rapid laser-assisted HCI transistor aging can selectively degrade transistors of individual functional IC blocks within an IC device.

An ultrasonic testing device having a packaged semiconductor device as a testing target, the device including: an ultrasonic oscillator disposed to face the semiconductor device; a pulse generator generating a driving signal that is used in the generation of an ultrasonic wave to be output from the ultrasonic oscillator; and an analysis unit analyzing an output signal that is output from the semiconductor device in accordance with the irradiation of the ultrasonic wave from the ultrasonic oscillator, in which the pulse generator sets an optimal frequency of the driving signal such that the absorption of the ultrasonic wave in the semiconductor device is maximized.

The invention provides a method for checking a semiconductor switch for a fault, wherein the semiconductor switch is driven with a PWM signal with a variable duty cycle. To the benefit of determining faults on the semiconductor switch reliably and cost-effectively, it is provided that if the semiconductor switch is operated with a duty cycle of 100% or 0%, the current measurement of the overall system is evaluated, while if the semiconductor switch is operated with a duty cycle of between 0% and 100%, the generated voltage pulses across the semiconductor switch are evaluated.

A control method includes: determining a first state of a plurality of components in an electronic device; acquiring a first operating state of the electronic device; and determining whether to allow one or more of the plurality of components to be removed based on the first state of the plurality of components and the first operating state of the electronic device.

A bonded structure is disclosed. The bonded structure can include a first element that has a first plurality of contact pads. The first plurality of contact pads includes a first contact pad and a second redundant contact pad. The bonded structure can also include a second element directly bonded to the first element without an intervening adhesive. The second element has a second plurality of contact pads. The second plurality of contact pads includes a third contact pad and a fourth redundant contact pad. The first contact pad is configured to connect to the third contact pad. The second contact pad is configured to connect to the fourth contact pad. The bonded structure can include circuitry that has a first state in which an electrical signal is transferred to the first contact pad and a second state in which the electrical signal is transferred to the second contact pad.

A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.

An aging detector for an electrical circuit component and a method for monitoring an aging of a circuit component includes an input of the aging detector recording a parameter of the circuit component, with the aging circuit being configured to, based on the recorded parameter, determine a corresponding response threshold and/or a response or adapt the response threshold and/or the response, and to initiate the response to the parameter exceeding the specific response threshold.