A semiconductor device comprises a power device, a sensor which measures a physical state of the power device to transmit a signal according to the physical state, and a main electrode terminal through which a main current of the power device flows. The semiconductor device further comprises a sensor signal terminal connected to the sensor for receiving a signal from the sensor, a driving terminal which receives driving power for driving the power device, and an open bottomed case which houses the power device, the sensor, the main electrode terminal, the sensor signal terminal and the driving terminal. The first and second terminals electrically conduct with each other to form a double structure. Also, the sensor signal terminal and the driving terminal each have a first terminal and a second terminal which are not embedded within the case.

A circuit device can be implemented, which includes a zener diode barrier composed of one or more zener diodes. The circuit device further includes one or more detection circuits electronically in series with the zener diode (or zener diodes) of the zener diode barrier. The zener diode barrier functions as an IS (Intrinsically Safe) barrier. The detection circuit (or circuits) facilitates the production of detailed information concerning different types of events detected by the detection circuit(s).

Methods and systems for optically determining the performance of active components of a device under test (DUT). A portion of the DUT that includes a target active component and an additional active component is illuminated and reflected energy from the target active component and the additional active component is detected by one or more sensors. An analog signal that corresponds to the reflected energy is generated by a processor. An estimated target signal determined based on the analog signal and the second analog signal, where the estimated target signal corresponds to an estimated component of the analog signal that is attributable to the target reflected energy reflected by the target active component. The estimated target signal is then used to determine the performance of the target active component of the DUT.

A test structure for measuring static noise margin (SNM) for one or more static random access memory (SRAM) cells can include a first transistor gate (TG) and a second TG electrically coupled to each SRAM cell. In an implementation, an interconnect between an output of a first inverter and an input of a second inverter of the SRAM cell can be electrically disconnected using a cut off. During operation of the SRAM cell, internal storage nodes within the SRAM cell can be electrically coupled through the first TG and the second TG to, for example, external pins and to a test fixture. Electrical parameters such as voltage can be measured at the internal storage nodes through the external pins and used to calculate SNM of the SRAM cell.

A testing system for carrying out electrical testing of at least one first through via forms an insulated via structure extending only part way through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the insulated via structure. The first electrical test circuit enables detection of at least one electrical parameter of the insulated via structure.

Monolithic three-dimensional integration can achieve higher device density compared to 3D integration using through-silicon vias. A test solution for M3D integrated circuits (ICs) is based on dedicated test layers inserted between functional layers. A structure includes a first functional layer having first functional components of the IC with first test scan chains and a second functional layer having second functional components of the IC with second test scan chains. A dedicated test layer is located between the first functional layer and the second functional layer. The test layer includes an interface register controlling signals from a testing module to one of the first test scan chains and the second test scan chains, and an instruction register connected to the interface register. The instruction register processes testing instructions from the testing module. Inter-layer vias connect the first functional components, the second functional components, and the testing module through the test layer.

A semiconductor device is disclosed including a stack of wafers having a densely configured 3D array of memory die. The memory die on each wafer may be arranged in clusters, with each cluster including an optical module providing an optical interconnection for the transfer of data to and from each cluster.

A control method includes: determining a first state of a plurality of components in an electronic device; acquiring a first operating state of the electronic device; and determining whether to allow one or more of the plurality of components to be removed based on the first state of the plurality of components and the first operating state of the electronic device.

A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.

There is provided an intermediate connection member provided between a first member having a plurality of first terminals and a second member having a plurality of second terminals to electrically connect the plurality of first terminals and the plurality of second terminals, respectively. The intermediate connection member includes: a block member including connection members configured to electrically connect the plurality of first terminals and the plurality of second terminals, respectively; a frame member having an insertion hole into which the block member is inserted; and an electronic component electrically connected to one of the connection members.