The disclosure provides an online test data record and offline data conversion analysis system and a method thereof. In the present disclosure, the test process information of the production line testing system performed on the circuit board to be tested is generated into online test result data in a database file format, and the offline analysis system receives the online test data from the production line testing system. The offline analysis system reads the corresponding data in the online test result data according to the designated data in the data designated instruction, and generates the offline test result data in the designated file format of the data designated instruction, and the offline analysis system perform the data analysis for the offline test result according to the analysis instruction.

In described examples, an SoC includes at least two voltage domains interconnected with a communication bus. Detection logic in a first voltage domain determines when a voltage error occurs in a second voltage domain and isolates communication via the communication bus when a voltage error or a timing error is detected.

System and method for autonomous trouble shooting of a unit under test (UUT) having a plurality of replaceable components include: a test station that stores an artificial intelligence (AI) program and a knowledge database (KDB) including acceptable test results for each test point represented by an acceptable test vector, a test probe to test the circuit card assembly; and an operator station to send commands to the test station via the communication network to teach the AI program to capture and store the acceptable test result for each test point of the UUT by the test probe, in the KDB, wherein the AI program commands the test probe to test the UUT, stores the test results in a test result vector, compares the test result vector with the stored acceptable test vector, and displays recommendation as which replaceable component in the UUT to be repaired or replaced.

A self-check system and a method thereof are disclosed. In the self-check system, a memory stores a safety check program, a main application program and a predetermined checksum data. The safety check program include a circuit check program, a watchdog circuit reset program and a checksum check program. When a chip system is powered on, a processing unit executes the main application program, and then executes an interrupt call to generate an interrupt, so as to execute the safety check program and the circuit check program to check a to-be-checked circuit. The processing unit also executes the watchdog circuit reset program to reset a counting value of a watchdog circuit. The processing unit also executes the checksum check program to calculate a checksum data of the first safety check program, and reset the chip system when the calculated checksum data is not equal to the predetermined checksum data.

A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.

An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.

An exemplary method of detecting a Trojan circuit in an integrated circuit is related to applying a test pattern comprising an initial test pattern followed by a corresponding succeeding test pattern to a golden design of the integrated circuit, wherein a change in the test pattern increases side-channel sensitivity; measuring a side-channel parameter in the golden design of the integrated circuit after application of the test pattern; applying the test pattern to a design of the integrated circuit under test; measuring the side-channel parameter in the design of the integrated circuit under test after application of the test pattern; and determining a Trojan circuit to be present in the integrated circuit under test when the measured side-channel parameters vary by a threshold.

An integrated circuit chip comprising: system circuitry comprising interconnect circuitry for transporting transactions; and monitoring circuitry configured to: monitor transactions from the interconnect circuitry comprising transactions between an entity and a specified region of the integrated circuit chip, the entity being associated with a set of one or more access rights for accessing the specified region of the integrated circuit chip; determine from the monitored transactions values of one or more parameters associated with the access to the specified region by the entity to identify whether the entity has breached its access rights; and perform a dedicated action indicative of a breach of the access rights in response to determining from the parameter values that the entity has breached its access rights.

An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor configurable as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a block to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed TO interface in response to the functional safety system entering an infield test mode.

In accordance with at least one aspect of this disclosure, a failure detection system for an integrated circuit component includes an integrated circuit component configured to connect to a circuit board, a first sensor operatively connected to sense and output a signal indicative of an actual current output of the component in a first state, and a second sensor operatively connected to sense and output a signal indicative of an actual condition of the component in the first state. A logic module can be configured to output a component failed state signal based at least in part on the signal indicative of the actual current output of the component in the first state and the signal indicative of the actual condition of the component in the first state.