An inspection data output device according to an embodiment includes an input unit, a generation unit, and an output unit. Information on a portion to be inspected in a circuit board is supplied to the input unit. The generation unit generates emphasis data in which an output signal path being a signal path on the circuit board and being a signal path capable of detecting an output signal of the portion to be inspected is emphasized more than another signal path. The output unit outputs the emphasis data to a display device.

A test device, an electronic device, and an operating method of the test device are provided. The test device schedules an execution order of test operations on target semiconductor intellectual properties (IPs), based on metadata and instruction data, the metadata including a dependency relationship indication between a plurality of semiconductor IPs and a time-out time of the test operation on each of the semiconductor IPs, and the instruction data including an operation and an address of each target semiconductor IP and a test sample, and perform the test operations on the target semiconductor IPs in the scheduled execution order.

A self-check system and a method thereof are disclosed. In the self-check system, a memory stores a safety check program, a main application program and a predetermined checksum data. The safety check program include a circuit check program, a watchdog circuit reset program and a checksum check program. When a chip system is powered on, a processing unit executes the main application program, and then executes an interrupt call to generate an interrupt, so as to execute the safety check program and the circuit check program to check a to-be-checked circuit. The processing unit also executes the watchdog circuit reset program to reset a counting value of a watchdog circuit. The processing unit also executes the checksum check program to calculate a checksum data of the first safety check program, and reset the chip system when the calculated checksum data is not equal to the predetermined checksum data.

In described examples, an SoC includes at least two voltage domains interconnected with a communication bus. Detection logic in a first voltage domain determines when a voltage error occurs in a second voltage domain and isolates communication via the communication bus when a voltage error or a timing error is detected.

In one embodiments, a system comprises: a plurality of scan test chains configured to perform test operations at a first clock speed; a central test controller for controlling testing by the scan test chains; and an interface configured to generate instructions to direct central test controller. The interface communicates with the centralized test controller at the first clock speed and an external scan input at a second clock speed. The second clock speed can be faster than the first clock speed. The instructions communicated to the central controller can be directions associated with sequential scan compression/decompression operations. In one exemplary implementation, the interface further comprise a mode state machine used to generate the mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.

An apparatus includes a test head frame and a tray slidably coupled to the frame and configured to receive a printed circuit board (PCB) to be tested. The PCB is positioned within the frame when the tray is in a retracted position and outside the frame when the tray is in an ejected position. A bed of nails (BON) opposes a lower side of the PCB and includes a plurality of pins having first portions arranged on an upper side of the BON to connect with corresponding electrical pads on the lower side of the PCB when the tray containing the PCB is in the retracted position. A plurality of interface printed circuit boards is configured for connection to second portions of the plurality of pins exposed on a lower side of the BON and for receiving test signals when the tray containing the PCB is in the retracted position.

A method for generating a validation test, may include obtaining, using a processor, a validated scenario for generating a test for a verification model, the validated scenario represented in the form of a directed acyclic graph with a plurality of actions as nodes of the graph. The method may also include analyzing, using the processor, the graph to identify an action of said plurality of actions designed to be executed on a thread that is associated with a faulty scheduler of a verification model to be tested. The method may further include, upon identifying the identified action, amending, using the processor, the verified scenario by removing the identified action from the graph.

A multi-chip package capable of testing internal signal lines including a printed circuit board, a first semiconductor chip mounted on the printed circuit board and including a test circuit, and second semiconductor chips mounted on the printed circuit board and electrically connected to the first semiconductor chip via a plurality of internal signal lines may be provided. The test circuit may be configured to enable circuits of the first semiconductor chip connected to pads contacting the plurality of internal signal lines, transmit complementary data to at least two pads from among the pads, and form a current path in the circuits connected to the at least two pads, thereby detecting a short-circuit between the internal bonding wires.

A display device and a testing method for a display panel are provided. The testing method for the display panel includes the steps of: storing an image signal for controlling the display panel to display a default image in a driver chip of the display panel, providing a power signal and a clock signal to the display panel, and retrieving the image signal and testing the display panel according to a preset test condition.

An isolation system includes a transmit die and a receive die coupled by an isolation channel. The transmit die receives diagnostic data at an input terminal and transmits the diagnostic data over an isolation channel to a receive die. The receive die supplies a signal from an internal node in the receive die identified by the diagnostic data to an output terminal of the receive die. Other diagnostic data received by the transmit die causes the transmit die to supply a signal from an internal node in the transmit die to a terminal of the transmit die.