G01R31/2805

SIGNAL PROCESSING METHOD
20220003804 · 2022-01-06 ·

A signal processing method is provided. The signal processing method is used in a Gigabit Ethernet system including a device under test (DUT) and a link partner (LP), and includes the following steps. Firstly, an interference detector is configured to detect whether the Gigabit Ethernet system is interfered by other signal sources. Next, a physical layer (PHY) of the DUT or a PHY of the LP is used to, in response to the Gigabit Ethernet system being interfered by the other signal sources, set a request signal indicating whether or not the physical layer enters a low power idle (LPI) mode as FALSE. Which PHY of the DUT and the LP is used to set the request signal indicating whether or not the PHY enters the LPI mode as FALSE depends upon which one of the DUT and the LP is provided with the interference detector.

Method for faster testing of manufactured PCB, apparatus, system, and storage medium used in method

A method for testing mass-produced PCBs and other electronic components more efficiently, the method includes setting testing parameters based on historical test data and a target decision index, obtaining a first specified number of the target objects to have the full test, and calculating a first yield based on the current test result. The method determine whether the first yield is less than the first yield threshold yield, and obtaining a second specified number of the target objects from the remaining target objects to have the full test, and calculate a second yield when the first yield is larger than or equal to the first yield threshold value. The method further determine whether the second yield is less than the second yield threshold value according to a second comparing command and select some of the remaining target objects to have a sampling test.

HOT E-TEST FOR UNPOPULATED PRINTED CIRCUIT BOARDS

The present invention relates to a test method for an unpopulated printed circuit board, comprising the steps of: exposing the unpopulated printed circuit board to temperatures of a reflow soldering process in a first step; and testing the electrical connections of the unpopulated printed circuit board. The present invention further relates to a test device and a method for producing populated printed circuit boards.

Device and Method for Measuring Thickness of Dielectric Layer in Circuit Board
20220221262 · 2022-07-14 ·

A method for measuring thickness of dielectric layer in circuit board includes the following steps: First, circuit board including dielectric layer and circuit layers is provided. The dielectric layer is between the circuit layers, and the circuit board further includes test area including test pattern and through hole. The test pattern includes first conductor and second conductors. The distance between the side of the through hole and the second conductor is less than the distance between the side of the through hole and the first conductor. Next, measuring device including conductive pin and sensing element is provided. Next, the conductive pin is powered, and one end of the conductive pin is electrically connected to the second conductor. Next, the sensing element is moved along the through hole to obtain sensing curve, and the thickness of the dielectric layer is calculated via variations of the sensing curve.

SYSTEM AND METHOD FOR DETECTING DEFECTIVE BACK-DRILLS IN PRINTED CIRCUIT BOARDS

The present invention provides a method for detecting failed back-drills in PCBs in the process of fabricating a PCB so that the failed back-drill can be screened out or repaired. The present invention accomplishes this by adding a short to ground connection for every back-drill via that will be cut when the back-drill removes the via stub. If the back-drill is bad or failed the short to ground will fail the subsequent electrical tests. The PCB can be repaired by re-drilling the hole or via. The present invention allows for detecting failed back-drills with easy detection in the manufacturing stage using standard equipment and test procedures. This process creates a simple pass-fail measurement that uses an existing common test process to catch failed back drills in the PCB fabrication facility. This allows for easy and cost-effective repair and guarantees back-drill failures do not pass into the field.

Adjustable probe device for impedance testing for circuit board

An adjustable probe device includes fixed and movable probes, at least one of which is a signal probe having a coaxial structure. The movable probe is linearly slidable with a ground unit thereof abutted against a ground unit of the fixed probe. Another adjustable probe device includes a first movable probe for being grounded, and fixed and second movable probes both having a coaxial structure. Any of the two movable probes is selectable to be a functioning probe in a way that the contact ends of the functioning and fixed probes are located on a same plane for contacting two pads of a DUT at the same time, and the functioning probe is linearly slidable with a ground unit thereof abutted against a ground unit of the fixed probe. As a result, the probe interval is adjustable, lowering the cost of the impedance testing apparatus for circuit boards.

Optimizing design and performance for printed circuit boards

A printed circuit board (PCB) includes a plurality of layers disposed at different depths of the PCB, circuit components disposed at different layers of the PCB, and a plurality of temperature measurement sensors located at one or more layers of the PCB, where each temperature measurement sensor is associated with a corresponding circuit component. A measured temperature is obtained at an embedded temperature measurement sensor located at an embedded layer within the PCB, and the measured temperature is correlated with an electrical property of an embedded circuit component located at the same embedded layer within the PCB as the embedded temperature measurement sensor. A plurality of moisture measurement sensors can also be located at one or more layers of the PCB to facilitate a measured moisture with an electrical property of an embedded circuit component.

Signal processing method

A signal processing method is provided. The signal processing method is used in a Gigabit Ethernet system including a device under test (DUT) and a link partner (LP), and includes the following steps. Firstly, an interference detector is configured to detect whether the Gigabit Ethernet system is interfered by other signal sources. Next, a physical layer (PHY) of the DUT or a PHY of the LP is used to, in response to the Gigabit Ethernet system being interfered by the other signal sources, set a request signal indicating whether or not the physical layer enters a low power idle (LPI) mode as FALSE. Which PHY of the DUT and the LP is used to set the request signal indicating whether or not the PHY enters the LPI mode as FALSE depends upon which one of the DUT and the LP is provided with the interference detector.

Device and method for measuring thickness of dielectric layer in circuit board

A method for measuring thickness of dielectric layer in circuit board includes the following steps: First, circuit board including dielectric layer and circuit layers is provided. The dielectric layer is between the circuit layers, and the circuit board further includes test area including test pattern and through hole. The test pattern includes first conductor and second conductors. The distance between the side of the through hole and the second conductor is less than the distance between the side of the through hole and the first conductor. Next, measuring device including conductive pin and sensing element is provided. Next, the conductive pin is powered, and one end of the conductive pin is electrically connected to the second conductor. Next, the sensing element is moved along the through hole to obtain sensing curve, and the thickness of the dielectric layer is calculated via variations of the sensing curve.

METHOD FOR IDENTIFYING PCB CORE-LAYER PROPERTIES
20220091181 · 2022-03-24 ·

A reference via in a set of plated vias on a printed circuit board is located. A reference lead is applied to the reference via. A test via in the set of plated vias is located. A test lead is applied to the test via. An electrical conductance between the reference via and the test via is measured. A property of a core layer of the printed circuit board is identified based on the electrical conductance.