The present disclosure provides a test probe and an apparatus for testing a printed circuit board, wherein the test probe comprises a test pin; and an insulating protection sleeve with adhesive attached therein, wherein the insulating protection sleeve is sleeved on the test pin, and wherein a first end of the test pin protrudes from the insulating protection sleeve.

An apparatus for detecting a wiring short in a substrate includes a voltage source configured to apply a rising or falling measurement voltage to a first wiring of a substrate, a plurality of electrodes including first and second electrode elements capacitively coupled to the first and second wirings of the substrate, respectively, a sensing circuit configured to generate an output voltage based on a voltage or a current between the first and second electrode elements, and a processor configured to determine whether a short circuit connection having a resistance value greater than a reference resistance value is present between the first and second wirings based on a change rate of the output voltage after application of the measurement voltage. Methods for detecting wiring shorts in the substrate are further provided.

A measuring system and method is configured to analyze numerous different types of interconnects having varying degrees of complexity. The measuring system and method characterizes an interconnect to be tested by a predefined reflection coefficient signature. Each specific interconnect is predefined by a reflection coefficient signature that is unique to that specific interconnect. Once the reflection coefficient signature is defined, a corresponding reflection envelope is defined which defines boundary limits about the reflection coefficient signature. Subsequent testing of the specific interconnect results in a measured reflection coefficient curve, which is compared to the corresponding reflection envelope. The specific interconnect under test is considered acceptable if the values of the measured reflection coefficient curve do not fall outside the reflection envelope. If one or more values of the measured reflection coefficient curve fall outside the reflection envelope, then the specific interconnect under test fails the test.

An apparatus for producing a printed circuit board on a substrate, has a table for supporting the substrate, a function head configured to effect printing conductive and non-conductive materials on the substrate, a positioner configured to effect movement of the function head relative to the table, and a controller configured to operate the function head and the positioner to effect the printing of conductive and non-conductive materials on the substrate. The apparatus optionally has a layout translation module configured to convert PCB files or multilayer PCB files to printing data for controlling the function head to print conductive material and nonconductive material onto the substrate. The apparatus has a testing head to verify conductors which operates automatically. The translation module also prints nonconductive material component alignment areas and nonconductive material substrate stiffeners.

A printed wiring board includes: a laminated body that has a plurality of wiring layers laminated therein; a first through hole that electrically connects two or more wiring layers with each other; and a second through hole that has strength to expansion and contraction of the laminated body less than in the first through hole.

Embodiments relate to a test method for testing an unpopulated printed circuit board. The method can involve the steps of: exposing the unpopulated printed circuit board to temperatures of a reflow soldering process in a first step; and testing the electrical connections of the unpopulated printed circuit board. Embodiments also relate to a test device and a method for producing populated printed circuit boards.

A test station and method of testing a design under test are disclosed. One method includes applying a first test frequency signal to a reference path to determine a first known attenuation level, and applying the first test frequency signal to a design under test to determine a first tested attenuation level of the design under test at the first test frequency. The method also includes applying a second test frequency signal to the reference path to determine a second known attenuation level, and applying the second test frequency signal to the design under test to determine a second tested attenuation level of the design under test at the second test frequency. The method includes determining whether the design under test is faulty based on the first tested attenuation level and the second tested attenuation level.

The present disclosure provides a wire detection device and a wire detection method. The wire detection device includes: a chamber body including a first side and a second side arranged opposite to each other; an electrode arranged at the second side of the chamber body; particles arranged within the chamber body; and a signal applying circuit configured to apply an electric signal to at least one wire to be tested arranged at the first side.

A printed circuit board (PCB) test coupon for thermal exposure and electrical testing includes a double sided or multi-layer substrate with a plurality of vias formed within the substrate of the test coupon (blind, buried, stacked vias) or extending through the entire substrate (through hole/via) from a first surface on the first side of the plated hole/via to a second surface on the second side of the plated hole/via. Each of a first plurality of trace patterns interconnect a subset of the plurality of plated holes/vias on the first side of the plated holes/vias, and each of a second plurality of trace patterns interconnect a different subset of the plurality of plated holes/vias on the second side of the plated holes/vias. The first and second pluralities of trace patterns have different patterns and connect to connection points in a connector pattern defined in the substrate. One of the second plurality of trace patterns is configured to measure temperature and two of the second plurality of trace patterns are configured to measure calibration/drift by resistance measurements. The test coupon provides test nets that include a single plated hole/via, and optionally includes daisy chain test nets. A resistance measurement of each plated hole/via (or daisy chain) is provided by connecting 2 wires of a 4-wire kelvin bridge measurement system to the first and second sides of the plated hole/via (or daisy chain) using connection points for one of the first plurality of trace patterns and one of the second plurality of trace patterns that connect to each side of the said plated hole/via (or daisy chain).

A printed circuit board (PCB) test coupon for thermal exposure and electrical testing includes a double sided or multi-layer substrate with a plurality of vias formed within the substrate of the test coupon (blind, buried, stacked vias) or extending through the entire substrate (through hole/via) from a first surface on the first side of the plated hole/via to a second surface on the second side of the plated hole/via. Each of a first plurality of trace patterns interconnect a subset of the plurality of plated holes/vias on the first side of the plated holes/vias, and each of a second plurality of trace patterns interconnect a different subset of the plurality of plated holes/vias on the second side of the plated holes/vias. The first and second pluralities of trace patterns have different patterns and connect to connection points in a connector pattern defined in the substrate. One of the second plurality of trace patterns is configured to measure temperature and two of the second plurality of trace patterns are configured to measure calibration/drift by resistance measurements. The test coupon provides test nets that include a single plated hole/via, and optionally includes daisy chain test nets. A resistance measurement of each plated hole/via (or daisy chain) is provided by connecting 2 wires of a 4-wire kelvin bridge measurement system to the first and second sides of the plated hole/via (or daisy chain) using connection points for one of the first plurality of trace patterns and one of the second plurality of trace patterns that connect to each side of the said plated hole/via (or daisy chain).