Patent classifications
G01R31/2806
Flying probe electronic board tester, and test method thereof
Machine with flying probes for testing electronic boards comprising a conveyor for loading/unloading the boards into/from the testing station, a plurality of flying probes suitable to interact with predetermined points of each board and a plurality of contacting devices arranged at the sides of the working volume of the flying probes and suitable to cooperate with contact areas arranged on one edge of the board.
METHOD AND DEVICE FOR ELECTRICAL TESTING OF AN ELECTRICAL ASSEMBLY
The present invention relates to a method for electrical testing of an electrical circuit for defects, all electrical or electronic parts are measured simultaneously, so an electrical image of the electrical circuit is received by a control/evaluation unit, in which an electrical excitation signal of an electrical current or an electrical voltage is applied simultaneously by the control/evaluation unit and a plurality of driver circuits at a plurality of test points of the electrical circuit, which test points may be arranged in any way. The electrical excitation signals applied via the driver circuits differ with regard to their spectral characteristic. The electrical current flowing in the particular test point and the resultant electrical voltage are recorded synchronously with regard to a waveform in relation to an electrical ground potential, and subsequently parameters of the parts and their electrical connections are calculated by the control/evaluation unit.
Measurement apparatus with projected user interface
A measurement apparatus (1) comprising at least one shielded electronic measurement circuit (2) configured to measure and process electrical signals and a user interface (6) used by a user to interact with the electronic measurement circuits (2) of said measurement apparatus (1), wherein the user interface (6) comprises at least one adaptable graphical user interface (6A) projected by a projection unit (7) of said measurement apparatus on one or several projection areas.
MARKING DEVICE FOR MARKING CIRCUIT BOARDS TESTED BY MEANS OF A TEST DEVICE
The invention relates to a marking device (02) for marking circuit boards (04) tested by means of a test device (01, 08), wherein the marking device (02) can be fixed to the test device (01, 08) in a defined target position, and wherein the marking device (02) has a marking member (06) which can engage the surface (05) of a circuit board (04), and wherein the marking member (06) can be driven by a drive mechanism (16) in order to apply a marking to the surface (05) of the circuit board (04) by an operating movement of the marking member (06) depending on the test result. The marking device (02) includes a fixation module (10) and a quick change module (11), wherein the marking device (02) can be fixed to the test device (01, 08) in the defined target position by means of the fixation module (10), and wherein the quick change module (11) includes the marking member (06) and the drive mechanism (16), and wherein the quick change module (11) can be replaced without removing the fixation module (10).
THROUGH-SILICON VIA CRACK DETECTING APPARATUS, DETECTING METHOD, AND SEMICONDUCTOR DEVICE FABRICATION METHOD HAVING THE SAME
The present disclosure relates to a through-silicon via (TSV) crack detecting apparatus, a detecting method, and a fabricating method of the semiconductor device. The TSV crack detecting apparatus includes a test TSV, a conductive liner, a second dielectric liner, a first contact, and a second contact. The test TSV is disposed within a semiconductor substrate, including a conductive channel and a first dielectric liner for isolating the conductive channel and the semiconductor substrate. The conductive liner surrounds the first dielectric liner. The second dielectric liner surrounds the conductive liner. The first contact is connected to the conductive channel. The second contact is connected to the conductive liner. A voltage difference between the first contact and the second contact is used to determine whether a TSV within a predetermined range to the test TSV has a crack based on a conductive state between the first contact and the second contact.
METHOD, SYSTEM AND PROBE FOR MEASURING AND VISUALIZING VALUES OF AN ELECTROMAGNETIC PARAMETER OF A PCB
Method, system and probe for visualizing measured values of an electromagnetic parameter of a PCB. A probe head of a probe contactless measures values of at least one electromagnetic parameter at at least two different positions of the PCB, a camera fixed in position relative to the probe head records for each of the different positions an image of an area of the PCB around the probe head, for each of the different positions, the measured value of the electromagnetic parameter is correlated with the recorded image of the area of the PCB around the probe head, a location of each of the recorded images of the areas on a map representation of the PCB is determined, the map representation of the PCB with the measured values of the electromagnetic parameter, and the map representation of the PCB is visualized together with the superimposed measured values of the electromagnetic parameter.
AUTOMATIC CIRCUIT BOARD TEST SYSTEM AND AUTOMATIC CIRCUIT BOARD TEST METHOD APPLIED THEREIN
An automatic circuit board test system includes at least one switch module of board under test connected with a test board, a control module and a test process module. The test board includes a first signal interface, a second signal interface and a third signal interface and a repeater. The second signal interface and the third signal interface are mutually connected by a signal cable. The first signal interface is connected with the repeater. The at least one switch module of board under test is connected with the second signal interface and the third signal interface. The control module is connected with the at least one switch module of board under test. The control module controls the at least one switch module of board under test. The test process module is connected with the control module and the first signal interface by at least two serial port buses.
System and method for remote intelligent troubleshooting
System and method for autonomous trouble shooting of a unit under test (UUT) having a plurality of replaceable components include: a test station that stores an artificial intelligence (AI) program and a knowledge database (KDB) including acceptable test results for each test point represented by an acceptable test vector, a test probe to test the circuit card assembly; and an operator station to send commands to the test station via the communication network to teach the AI program to capture and store the acceptable test result for each test point of the UUT by the test probe, in the KDB, wherein the AI program commands the test probe to test the UUT, stores the test results in a test result vector, compares the test result vector with the stored acceptable test vector, and displays recommendation as which replaceable component in the UUT to be repaired or replaced.
Method and apparatus for flexure testing of electronic components
Disclosed herein is a method and apparatus for testing the response of electrical circuits to being flexed. Support members, preferably at least two, are positioned to receive the electrical circuits to be tested. The support members are spaced apart from each other to permit the electrical circuit to be flexed between the two support members. A plunger, having an arcuate front face is positioned between the support members. The plunger is depressed, flexing the electrical circuit a selected amount. After the circuit has been flexed a selected amount, the circuit is tested to determine whether or not it is fully operational after being flexed.
TEST DEVICE, ELECTRONIC DEVICE, AND OPERATING METHOD OF TEST DEVICE
A test device, an electronic device, and an operating method of the test device are provided. The test device schedules an execution order of test operations on target semiconductor intellectual properties (IPs), based on metadata and instruction data, the metadata including a dependency relationship indication between a plurality of semiconductor IPs and a time-out time of the test operation on each of the semiconductor IPs, and the instruction data including an operation and an address of each target semiconductor IP and a test sample, and perform the test operations on the target semiconductor IPs in the scheduled execution order.