In a contact terminal, the first insertion portion includes a first contact portion having a first flat surface along an axial direction, the second insertion portion includes a second contact portion having a second flat surface along the axial direction, the first flat surface and the second flat surface are in contact with each other, the tubular body includes at least one of a first end side notch provided along the axial direction on a peripheral surface of the one end portion in the axial direction of the tubular body and a second end side notch provided along the axial direction on a peripheral surface of the other end portion in the axial direction of the tubular body.

Apparatuses for characterizing system channels and associated methods and systems are disclosed. In one embodiment, a tester is coupled to an adaptor configured to plug into a CPU socket of a system platform (e.g., a motherboard). The motherboard includes a memory socket that is connected to the CPU socket through system channels. The adaptor may include a connector configured to physically and electrically engage with the CPU socket, an interface configured to receive test signals from the tester, and circuitry configured to internally route the test signals to the connector. The adaptor, if plugged into the CPU socket, can facilitate the tester to directly assess signal transfer characteristics of the system channels. Accordingly, the tester can determine optimum operating parameters for the memory device in view of the system channel characteristics.

A radio frequency circuit includes a base plate, an element under test, a transmission line, a sensing line, and a controller. The base plate has a first surface. The element under test is disposed on the base plate and includes an output port to output an RF signal. The transmission line is disposed on the first surface of the base plate and electrically connected to the output port of the element under test. The sensing line is substantially parallel to the transmission line within a sensing area of the base plate. The sensing line is separated from the transmission line by a first length and adapted for inducing the RF signal on the transmission line to generate an induction signal. The controller is disposed on the base plate, electrically connected to the sensing line, and configured to determine the state of the element under test according to the induction signal.

A semiconductor device 1a includes: a first external terminal 31 to which a first voltage is to be applied; a second external terminal 32 to which a second voltage is to be applied; a third external terminal 33; first wiring 17 connected to the first external terminal 31; second wiring 18 connected to the second external terminal 32; an internal block circuit 11 connected to the first wiring 17; a first resistor 12 and a transistor 14 serially connected between the first wiring 17 and the second wiring 18; and a second resistor 13 connected between the first wiring 17 and the second wiring 18. The transistor 14 turns on or off based on a test signal fed from the third external terminal 33. This configuration enables product identification using a resistance value, even if a predetermined resistance value cannot be changed.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a flexible sideband support system comprises a load board, testing electronics coupled to the load board, a controller coupled to the testing electronics. The load board is configured to couple with a plurality of devices under test (DUTs), wherein the load board includes in-band testing ports and sideband testing ports. The testing electronics is configured to test the plurality of DUTs, wherein a portion of testing electronics are organized in sideband resource groups. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics and the controller directs selective allocation of the testing electronics in the sideband resource groups to various testing operations of the DUTs. In one exemplary implementation, the controller directs a portion of sideband testing of a plurality of DUTs concurrently.

A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.

Apparatuses for characterizing system channels and associated methods and systems are disclosed. In one embodiment, a tester is coupled to an adaptor configured to plug into a CPU socket of a system platform (e.g., a motherboard). The motherboard includes a memory socket that is connected to the CPU socket through system channels. The adaptor may include a connector configured to physically and electrically engage with the CPU socket, an interface configured to receive test signals from the tester, and circuitry configured to internally route the test signals to the connector. The adaptor, if plugged into the CPU socket, can facilitate the tester to directly assess signal transfer characteristics of the system channels. Accordingly, the tester can determine optimum operating parameters for the memory device in view of the system channel characteristics.

A test fixture for coupling a Device Under Test (DUT) to a measurement instrument includes a device interface board, which may be a solderless, press-fit board, for electrically connecting to one or more DUTs, a power delivery section electrically coupled to the device interface board through a series of electrical contacts, a measurement interface section electrically coupled to the device interface board through a second series of electrical contacts, the measurement interface structured to be coupled to the measurement instrument, and a metal plate coupled between and providing an electrical return path between the measurement interface and the power delivery section. The metal plate is sized and shaped to provide physical protection from DUTs that are destroyed during testing.

An electronic device, which includes at least a first part and a second part bonded to each other is provided. The first part includes a first bonding area. The first bonding area includes at least one first testing area. The first testing area includes a plurality of testing pads. The second part includes a second boding area corresponding to the first bonding area. The second bonding area includes a plurality of testing terminals, and includes at least one second testing area respectively corresponding to the at least one first testing area. The second testing area includes a plurality of testing pins. The plurality of testing pads, the plurality of testing terminals and the plurality of testing pins are configured to form a current channel and a voltage testing channel, for measuring a resistance of bonded testing pads and testing pins on both the current channel and the voltage testing channel.

A printed circuit board (PCB) may include a signal layer having a functional region and a PCB signal layer testing region. The PCB signal layer testing region may include a first differential pair having a first length formed on the signal layer, a second differential pair having a second length, different than the first length, formed on the signal layer and a third differential pair having a third length, different than the first length and different than the second length, formed on the signal layer.