An electronic apparatus includes: an electronic module; and a flexible substrate electrically connected to the electronic module. The flexible substrate includes: a base film; a plurality of first contact pads arranged at one end on the base film in a first direction, and electrically connected to the electronic module; a plurality of second contact pads arranged at an other end on the base film in the first direction; a plurality of first wires arranged on the base film, and each electrically connecting one of the first contact pads and one of the second contact pads together; and a plurality of third contact pads arranged on the base film, each of the third contact pads being positioned along the first direction between one of the first contact pads and one of the second contact pads, and being electrically connected to one of the first wires.

A power semiconductor module arrangement includes: a housing; a substrate having a substrate layer and a first metallization layer on a first side of the substrate layer, inside the housing or forming a bottom of the housing; a printed circuit board inside the housing, vertically above and in parallel to the substrate; electrically conducting components on the printed circuit board and substrate; an encapsulant at least partly filling the interior of the housing; and a magnetic field sensor either on the substrate within range of a magnetic field caused by a current flowing through one of the electrically conducting components arranged on the printed circuit board, or on the printed circuit board within range of a magnetic field caused by a current flowing through one of the electrically conducting components arranged on the substrate. The magnetic field sensor is electrically insulated from the respective electrically conducting component.

A method for indicating a probing target for a fabricated electronic circuit including: generating an electronic, three-dimensional model based on manufacturing layout information of a fabricated circuit; obtaining, with a vision system, visual environment information for the fabricated circuit; scaling and orienting the three-dimensional model by a scaler and mapper based on the visual environment information; overlaying the three-dimensional model with the visual environment information to produce a correlated image; obtaining an identification of a desired network node of the fabricated circuit; and indicating a probing target, the probing target corresponding to the desired network node of the fabricated circuit.

An electronic device, which includes at least a first part and a second part bonded to each other is provided. The first part includes a first bonding area. The first bonding area includes at least one first testing area. The first testing area includes a plurality of testing pads. The second part includes a second boding area corresponding to the first bonding area. The second bonding area includes a plurality of testing terminals, and includes at least one second testing area respectively corresponding to the at least one first testing area. The second testing area includes a plurality of testing pins. The plurality of testing pads, the plurality of testing terminals and the plurality of testing pins are configured to form a current channel and a voltage testing channel, for measuring a resistance of bonded testing pads and testing pins on both the current channel and the voltage testing channel.

A method and apparatus for detecting an electrical fault in a printed circuit board includes a first conductive layer interconnecting a set of electrical components, a second conductive layer connected to an electrical ground, a set of fuses arranged about the printed circuit board, and a fault detection circuit electrically connected to the printed circuit board.

An electronic device according to various embodiments may include: a board; a communication circuit disposed on one face of the board and configured to process a communication signal in a designated frequency band; an antenna disposed on the one face of the board or inside the board; a connector disposed on another face of the board, and including a first contact electrically connected to a first signal path through which the communication circuit is configured to transmit a signal to the antenna in a first direction, and a second contact electrically connected to a second signal path through which the communication circuit configured to transmit a signal to the antenna in a second direction; and conductive pads disposed on the another face of the board spaced apart from the connector, and including at least two first pads corresponding to the first contact and at least two second pads corresponding to the second contact.

A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.

A circuit board and a method for electrical performance detection thereof, a display panel, a method for fabricating a display panel, and a method for driving the display panel are provided. In the electrical performance detection, the signal output terminal is electrically connected to the detection terminal, and detection is performed on the drive signal by the electrical performance detection circuit to determine whether the circuit board is abnormal, achieving the electrical performance detection of the circuit board. In addition, in a process other than the electrical performance detection, the signal output terminal is disconnected from the detection terminal to avoid affecting a normal operation of the circuit board. The electrical performance detection of the circuit board is realized, a defective circuit board is prevented from flowing into a subsequent fabricating procedure, and waste of assembling resources is avoided.

The present disclosure describes printed circuit board performance evaluation techniques. In some cases, a printed circuit board performance evaluation process may include determining a first set of electrical properties associated with an interface between components of a printed circuit board, where the interface is disposed on an internal or external layer of the printed circuit board. After selective application of a sheet of dielectric material to a portion of a transmission line in the interface, a second set of electrical properties associated with the interface may be determined. The first set of electrical properties may be compared to the second set of electrical properties to evaluate printed circuit board performance. In other cases, the interface may include a trace inductor, and electrical properties of the interface before and after application of a ferrous material may be compared to evaluate printed circuit board performance.

A reference via in a set of plated vias on a printed circuit board is located. A reference lead is applied to the reference via. A test via in the set of plated vias is located. A test lead is applied to the test via. An electrical conductance between the reference via and the test via is measured. A property of a core layer of the printed circuit board is identified based on the electrical conductance.