A circuit for detection and warning of electro-migration in a region on a printed circuit board between a first electrically conductive element having a first electrical characteristic and a second electrically conductive element having a second electrical characteristic different than the first. The circuit includes an electrically conductive guard track that is electrically isolated from the first and second elements in the region and has a normal condition electrical characteristic based on the first and second characteristics. The circuit includes an electrical characteristic supervisor to detect an electrical characteristic of the guard track. In response to electro-migration creating an electrical connection of the guard track to the first or second element, the guard track has an abnormal condition electrical characteristic different than the normal condition. In response to detecting the abnormal condition of the guard track, the supervisor effectuates a warning of electro-migration in the region.

An automatic circuit board test system includes at least one switch module of board under test connected with a test board, a control module and a test process module. The test board includes a first signal interface, a second signal interface and a third signal interface and a repeater. The second signal interface and the third signal interface are mutually connected by a signal cable. The first signal interface is connected with the repeater. The at least one switch module of board under test is connected with the second signal interface and the third signal interface. The control module is connected with the at least one switch module of board under test. The control module controls the at least one switch module of board under test. The test process module is connected with the control module and the first signal interface by at least two serial port buses.

Embodiments are generally directed to a buried electrical debug access port. An embodiment of an apparatus includes a substrate or printed circuit board; one or more electronic components coupled with the substrate or printed circuit board; one or more electrical access ports coupled with the substrate or printed circuit board, each electrical access port including electrically conductive material; and an encapsulant material, the encapsulant material encapsulating the one or more access ports, wherein the one or more access ports are electrically connected to one or more circuits of the apparatus to provide debugging access to the apparatus.

Provided is an electric connecting apparatus 10 including a plurality of probes 20, a probe substrate 16 connected to base end portions 20b of the probes 20, and a probe support body 18, when tip end portions 20a of the probes 20 are pressed by a device under test, preventing the adjacent probes 20 from interfering. The probe support body 18 includes a plate-like guide portion 30 including guide holes through which the probes 20 pass. The guide portion 30 includes an upper guide portion 31, a lower guide portion 32, and a middle guide portion 33. The probes pass through the guide holes of the upper guide portion 31, the middle guide portion 33, and the lower guide portion 32 to be guided toward the device under test. The middle guide portion 33 is provided to be movable in a perpendicular direction X perpendicular to a thickness direction Y.

System and method for autonomous trouble shooting of a unit under test (UUT) having a plurality of replaceable components include: a test station that stores an artificial intelligence (AI) program and a knowledge database (KDB) including acceptable test results for each test point represented by an acceptable test vector, a test probe to test the circuit card assembly; and an operator station to send commands to the test station via the communication network to teach the AI program to capture and store the acceptable test result for each test point of the UUT by the test probe, in the KDB, wherein the AI program commands the test probe to test the UUT, stores the test results in a test result vector, compares the test result vector with the stored acceptable test vector, and displays recommendation as which replaceable component in the UUT to be repaired or replaced.

A printed circuit board includes a substrate and at least one electrical circuit provided at least partially on a surface layer of the printed circuit board. The electrical circuit includes an electrical trace that is in electrical connection with a test pad provided for accessibility on the surface layer, the test pad being sized and shaped for probing to test an aspect of the circuit, the test pad having a conductive probe surface that is structured to provide at least one vertical surface that extends from the probe surface toward the surface layer and thus providing an edge between the vertical surface and the probe surface, the probe surface having a coating of a material to protect the conductive probe surface from corrosion.

An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.

An array substrate, a display panel, and a display device. The array substrate has a display area and a non-display area surrounding the display area. The array substrate further includes a plurality of signal lines located in the display area, a plurality of test signal lines and a plurality of test control transistors located in the non-display area and respectively corresponding to the plurality of signal lines. Each of the signal lines is connected to a respective one of the test signal lines by a respective one of the test control transistors. The plurality of test control transistors each have a channel width-to-length ratio between 10 and 200.

Method for estimating degradation of a wire-bonded power semiconductor module (1) comprising: a) obtaining an indicator of degradation (Degr.sub.est_t-1); b) estimating (11) an estimated indicator of degradation (Degr.sub.est_t) by a temporal degradation model; c) obtaining (3) a set of on-line measure (X.sub.on_meas_t); then, d1) converting (13) the on-line measure (X.sub.on_meas_t) into a deducted indicator of degradation (Degr.sub.meas_t) by an electrical equivalence model, and e1) computing (15) a deviation between estimated and deducted indicator of degradation (Degr.sub.est_t; Degr.sub.meas_t); and/or d2) converting (13) the estimated indicator of degradation (Degr.sub.est_1) into a set of on-line estimation (X.sub.on_est_t), and e2) computing (15) a deviation between set of on-line measure and estimation (X.sub.on_ meas_t; X.sub.on_est_t); and f) correcting (17) the estimated indicator of degradation (Degr.sub.est_t) into a corrected estimated indicator of degradation (Degr.sub.corr_t) in function of the computed deviation.

A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.