A wafer chip testing method and apparatus, an electronic device and a storage medium are provided. The testing method includes: comparing each configuration parameter of each wafer chip with a standard specification threshold interval of a corresponding parameter type, and marking as marked test parameters configuration parameters which do not belong to the standard specification threshold intervals; and inputting all marked test parameters of individual wafer chip into a combination rule judgment function respectively, outputting wafer chip(s) which does not conform to any one or more rules in the combination rule judgment function, and determining the wafer chip(s) as unqualified wafer chip(s).

A self-contained metrology wafer carrier systems and methods of measuring one or more characteristics of semiconductor wafers are provided. A wafer carrier system includes, for instance, a housing configured for transport within the automated material handling system, the housing having a support configured to support a semiconductor wafer in the housing, and a metrology system disposed within the housing, the metrology system operable to measure at least one characteristic of the wafer, the metrology system comprising a sensing unit and a computing unit operably connected to the sensing unit. Also provided are methods of measuring one or more characteristics of a semiconductor wafer within the wafer carrier systems of the present disclosure.

Various particular embodiments include a via testing structure, including: a first terminal coupled to a first set of sensing lines in a top level of the structure; a second terminal coupled to a second set of sensing lines in the top level of the structure, wherein first set of sensing lines and the second set of sensing lines are disposed in a comb arrangement; a third terminal coupled to a third set of sensing lines in a bottom level of the structure; and a plurality of vias electrically coupling the second set of sensing lines in the top level of the structure to the third set of sensing lines in the bottom level of the structure, each via having a via top and a via bottom.

A test system can receive a test signal from a device under test (DUI) via a first signal path. A comparator circuit can receive the test signal and, in response, generate an intermediate output signal based on a magnitude relationship between the test signal a comparator reference signal. A compensation circuit can generate a correction signal that is complementary to a portion of the received test signal, such as to correct for loading effects of the first signal path. The test system can include an output circuit configured to provide a corrected differential output signal that is based on a combination of the intermediate output signal and the correction signal.

A ring oscillator system for characterizing substrate strain including, a substrate including a through-substrate-via, at least two ring oscillators, wherein a first ring oscillator is closer to the through-substrate-via than a second ring oscillator, and a logic difference circuit that is configured to receive an input from at least the first ring oscillator and the second ring oscillator, and detect a difference between the signal frequency of the first ring oscillator and the signal frequency of the second ring oscillator.

A wafer probe test system has a conductive needle configured to contact a conductive feature on a surface of a wafer, and a fluid probe having a multichannel tube, the fluid probe configured to engage the surface of the wafer to form a fluidic seal between a sensor face on the surface of the wafer and the conductive feature of the wafer, the multichannel tube having a first channel and a second channel configured to create a flow of fluid across the sensor face on the surface of the wafer.

A system of inspecting a focus ring is provided. The system includes a measuring device, a transfer device and an operation unit. The measuring device includes a base substrate, a sensor chip and a circuit board. The sensor chip has a sensor electrode and is provided along an edge of the base substrate. The circuit board is configured to output a high frequency signal to the sensor electrode and acquire a digital value indicating electrostatic capacitance based on a voltage amplitude in the sensor electrode. The transfer device is configured to scan the measuring device. The operation unit is configured to obtain difference values by performing a difference operation with respect to the digital values acquired by the measuring device at multiple positions along a direction which intersects with an inner periphery of the focus ring.

Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.

A substrate is provided. The substrate includes a front region having a front surface, a back region having a back surface, an edge exclusion region, and a chamfered surface. The back surface is laterally opposite the front surface. The edge exclusion region is surrounding the front region. The chamfered surface is at least partially arranged in the edge exclusion region.

A semiconductor structure includes at least two via chains. Each via chain includes at least one first conductive component, at least one second conductive component and at least one via. The first conductive component has an axis along an extending direction of the first conductive component. The via connects the first conductive component to the second conductive component. The via has a center defining a shift distance from the axis of the first conductive component. The shift distances of the via chains are different. A testing method using such a semiconductor structure includes drawing a resistance-shift distance diagram illustrating a relationship between the resistances of the via chains and the shift distances of the via chains. At least one dimensional feature is obtained from the resistance-shift distance diagram.