A semiconductor test apparatus according to the present disclosure includes: a stage on which a wafer is to be mounted; a pressurizing wall disposed on a surface of a probe card opposing the stage, extending toward the stage, and having an opening; a mark disposed on a lower surface of the pressurizing wall opposing the stage; a probe disposed in the opening; an air tube to force air into the opening; a detector to detect first spacing between a tip of the probe and the mark; and a controller to control second spacing between the wafer and the lower surface of the pressurizing wall based on the first spacing, wherein, when an electrical property of each of chips of the wafer is measured, the second spacing is controlled to be predetermined spacing by the controller, and the air is forced into the opening through the air tube.

A wafer inspection method and inspection apparatus that perform a voltage inspection of a die on a wafer by a probe module. The probe module includes a processing module, a first probe coupled to a first electrode point of the die, and a second probe coupled to a second electrode point of the die. The first probe is coupled to the processing module, and the second probe is grounded. The processing module provides the die with a driving current through the first probe, and obtains an inspection voltage corresponding to the die. The processing module generates an inspection result of the inspection voltage based on two reference voltages respectively representing a high critical threshold value and a low critical threshold value of the die under a normal operation. The inspection result indicates an operating status of the die. Thus, inspection costs are reduced and inspection efficiency is enhanced.

Silicon test structures are described that enable separate measurement of n-channel metal-oxide semiconductor (NMOS) and p-channel metal-oxide semiconductor (PMOS) transistor delays. NMOS and PMOS specific non-inverting stages may be used to construct a multi-stage ring oscillator. Each of the non-inverting stages generates either a rising or falling primary transition that is determined by either NMOS or PMOS transistors, respectively. The opposing transition for a particular non-inverting stage is triggered by propagation of the primary transition to a subsequent non-inverting stage (producing a “reset” pulse). A frequency of the ring oscillator is determined by the primary transition and one transistor type (NMOS or PMOS). Specifically, the frequency is determined by the propagation delay of the primary transition through the entire ring oscillator.

The testing apparatus for singulated semiconductor dies comprises a nesting frame and a bottom part, which form a testing device nest adapted to the size of a semiconductor die. A pushing device is provided for an alignment of the semiconductor die in the testing device nest. An engineering plastic layer on the bottom part forms a surface on which the semiconductor die slides during its alignment.

A method of identifying defects in an electronic assembly, comprising, by a processing unit, obtaining a grid of nodes representative of a location of electronic units of an electronic assembly, wherein each node is neighboured by at most eight other nodes, wherein a first plurality of nodes represents failed electronic units according to at least one test criterion, and a second plurality of nodes represents passing electronic units according to the least one first test criterion, based on the grid, determining at least one first and second straight lines, and attempting to connect the first and second straight lines into a new line, wherein if at least one node from the new line belongs to the second plurality of nodes, concluding that an electronic unit represented by the node on the grid is a failed electronic unit, thereby facilitating identification of a failed electronic unit on the substrate.

A semiconductor wafer includes a scribe line and a probe pad. The scribe line extends along a first direction. The probe pad is disposed on the scribe line and is configured to contact a probe needle. The probe pad includes a first metal layer, a dielectric layer, and a second metal layer. The dielectric layer is disposed on the first metal layer, in which the dielectric layer includes a first recess and a second recess. The second metal layer is configured to connect to the first metal layer, in which the second metal layer includes a first portion and a second portion, and the first portion and the second portion are separated by a distance in a second direction perpendicular to the first direction.

A semiconductor substrate has an internal circuit, a plurality of first pads electrically connected to the internal circuit, and one or a plurality of second pads that have a surface hardness lower than that of the plurality of first pads and are not electrically connected to the internal circuit.

In a method of manufacturing an integrated circuit involving performing an electrostatic discharge (ESD) test, a weak frequency band is detected by sequentially radiating a plurality of first electromagnetic waves on a first test board including the integrated circuit. First peak-to-peak voltage signals are detected by sequentially radiating the plurality of first electromagnetic waves on a second test board including an electromagnetic wave receiving module. A frequency spectrum is detected by radiating a second electromagnetic wave on a housing including a third test board including the electromagnetic wave receiving module. A second peak-to-peak voltage signal is generated based on the weak frequency band, the first peak-to-peak voltage signals and the frequency spectrum. An ESD characteristic associated with an electronic system including the integrated circuit is predicted based on the second peak-to-peak voltage signal.

A burn-in board for testing the operational integrity of memory devices includes local heating elements for each memory device under test. Each socket on the burn-in board may include a pair of opposed latch heads which move between open positions allowing a memory device to be mounted in the socket, and closed positions where the latch heads rest against the memory device to secure the device in the socket. Local heating elements may be integrated into the latch heads to ensure even heating of each memory device in the burn-in board.

A temperature-control device (1) is provided for controlling the temperature of a prober table (110) for semiconductor wafers and/or hybrids. The device has a fluid inlet (10) for introducing a temperature-control fluid into the temperature-control device (1) and a first heat exchanger (20) for preliminary control of the temperature of the temperature-control fluid that is introduced. A second heat exchanger (30) is used to control the temperature of the temperature-control fluid. The temperature-controlled temperature-control fluid can be conducted to the prober table (110) through a prober temperature-control line (40). A return circuit (60) is configured, so that upon receiving a return switch signal, the return circuit (60) selectively either conducts a temperature-control fluid returned from the prober table (110) through the first heat exchanger (20) or allows the temperature control fluid to flow out bypassing the first heat exchanger (20).