A test method is disclosed. The test method includes the following operations: transmitting from a first controller a first command by a network to a test apparatus; the test apparatus being disconnecting from a prober in response to the first command received by a control interface in the test apparatus; controlling, by the control interface, at least one operation of the prober on a wafer held by the prober or a probe through a first control signal that is generated by the test apparatus to the prober and associated with the second command; and testing, by the prober and the test apparatus, the wafer and outputting a test data of the wafer.

A universal automatic test system for a digital plugboard based on imagine processing, including a digital plugboard test platform, an image acquisition and processing module, a test instrument module and a control and processing module.

Circuits and methods for improving IC yield during automated test equipment (ATE) calibration of circuit designs which require I.sub.DD calibration and use a closed feedback bias circuit, such as amplifier circuits. The circuit designs include bias branch/active circuit architectures where the active circuit includes one or more active devices. An example first embodiment uses an on-chip calibration switch between the on-chip grounds of a bias network and an active circuit comprising an amplifier. During calibration of the active circuit by the ATE, the calibration switch is closed, and after completion of calibration, the calibration switch is opened. An example second embodiment utilizes an active on-chip feedback loop calibration circuit to equalize voltages between the on-chip grounds of a bias network and an active circuit comprising an amplifier during calibration of the active circuit. Both embodiments mitigate or overcome miscalibration of active circuit current settings resulting from ATE test probe resistance.

A test and measurement system includes a test and measurement device configured to receive a signal from a device under test, and one or more processors configured to execute code that causes the one or more processors to generate a waveform from the signal, apply an equalizer to the waveform, receive an input identifying one or more measurements to be made on the waveform, select a number of unit intervals (UIs) for a known data pattern, scan the waveform for the known data patterns having a length of the number of UIs, identify the known data patterns as short pattern waveforms, apply a machine learning system to the short pattern waveforms to obtain a value for the one or more measurements, and provide the values of the one or more measurements for the waveform. A method includes receiving a signal from a device under test, generating a waveform from the signal, applying an equalizer to the waveform, receiving an input identifying one or more measurements to be made on the waveform, selecting a number of unit intervals (UIs), scanning the waveform to identify short pattern waveforms having a length equal to the number of UIs, applying a machine learning system to the short pattern waveforms to obtain a value for the one or more measurements, and providing the values of the one or more measurements for the waveform from the machine learning system.

An apparatus is provided that is implemented to enable multiple tests of different types, such as a direct current (DC) test and/or a radio frequency (RF) test of a semiconductor device. The apparatus includes a microelectromechanical systems (MEMS) switch block coupled between the semiconductor device and automatic testing equipment (ATE). The apparatus is configured to enable/disable a DC path or an RF path to switch between a DC test and an RF test without reconfiguring the connections between the semiconductor device and the ATE. The DC path is used to perform a DC contact test for one or more pins of the semiconductor device. The RF path is used to perform an RF test for the semiconductor device.

Embodiments of the present disclosure use a customizable ganged waveguide that comprises a top metal plate and a bottom metal plate with trenches that come together in a way so as to form waveguide channels. The waveguide assembly of the present invention also comprises a waveguide adapter affixed to a first end of the ganged waveguide and operable to conduct the signal to a tester. Further, it comprises an air barrier affixed to a second end of the ganged waveguide to prevent air from flowing from the ganged waveguide to a printed circuit board connected at the second end. Finally, it comprises a tuning plate comprising double ridge slots configured to allow maximal signal to be transferred to the printed circuit board from the ganged waveguide.

A device for generating waveforms includes a machine learning system configured to associate waveforms from a device under test to parameters, a user interface configured to allow a user to provide one or more user inputs, and one or more processors configured to execute code that causes the one or more processors to receive one or more inputs through the user interface that include one or more parameters, apply the machine learning system to the received one or more parameters, produce, by the machine learning system, a waveform based on the one or more parameters, and output the produced waveform. Methods of generating waveforms are also presented.

An automated test equipment for testing one or more DUTs comprises a test head and a DUT interface. The DUT interface comprises a plurality of blocks of spring-loaded pins, for example groups or fields of spring-loaded pins. For example, the DUT interface is configured for establishing an electronic signal path between the test head and a DUT board or load board, which holds the DUT or which provides a connection to the DUT. The automated test equipment is configured to allow for a variation of a distance between at least two blocks of spring-loaded pins.

An automated test equipment comprises a tester control configured to broadcast and/or specific upload to matching module input data and/or device-specific data including keys and/or credentials and/or IDs and/or configuration information. The automated test equipment further comprises a channel processing unit configured to transform input data using device specific data in order to obtain device-under-test adapted data for testing the device under test. The channel processing unit further configured to process the DUT data using device specific data in order to evaluate the DUT data. A method and a computer program for testing one or more devices under test in an automated test equipment are also disclosed.

An injection device is utilized to inject a liquid onto a test area of a semiconductor element. The injection device includes a height-adjusting base, a reservoir, a first testing pipe, a cleaning pipe, a liquid-draining pipe, and an electrode rod. The reservoir is provided with a dropping port. The dropping port is against the test area of the semiconductor element. The first testing pipe, the cleaning pipe and the liquid-draining pipe are connected to the reservoir. The electrode rod penetrates through the reservoir and contacts and ionizes a testing liquid. A semiconductor testing system utilizing the injection device and its testing method are also provided herein.