An apparatus is provided for testing a PCIe interface on a printed circuit assembly. The apparatus can include a plurality of electrical contacts to couple to a PCIe interface of the printed circuit assembly, wherein a respective electrical contact corresponds to a pin of the PCIe interface. The apparatus can also include a plurality of resistors. Each resistor is coupled between two adjacent electrical contacts. At least one electrical contact corresponds to a ground, power, or not connected (NC) pin of the PCIe interface, thereby allowing a loopback test to determine connectivity between the pins of the PCIe interface and the printed circuit assembly.

A circuit for calibrating a plurality of automated test equipment channels comprises a central measurement unit configured to provide a current to one of the ATE channels and/or to measure a current from one of the ATE channels. The central measurement unit comprises a central measurement port, which is coupled with the plurality of ATE channels via respective diodes circuited between the central measurement port of the central measurement unit and respective DUT ports of the ATE channels.

A test and measurement device has an interface, one or more connectors, each connector to allow the test and measurement device to connect to a test and measurement instrument, and one or more processors, the one or more processors configured to execute code to cause the one or more processors to: receive one or more user inputs through the interface identifying one or more tests to perform on a device under test (DUT); form a connection through one of the one or more connectors to the DUT to perform the one or more tests and receive test result data; apply one or more machine learning models to the test result data to identify potentially anomalous test results; and generate and present a representation of the test result data and the potentially anomalous test results. A method of analyzing test data includes receiving one or more user inputs through an interface identifying one or more test to perform on a device under test (DUT), forming a connection to at least one test and measurement instrument, directing the test and measurement instrument to perform one or more tests on the DUT and receive test result data, applying one or more machine learning models to the test result data to identify potentially anomalous test results, and generating and presenting a representation of the test result data and the potentially anomalous test results.

A multiple output isolated power supply for the usage as a floating V/I source in an automated test equipment. The multiple output isolated power supply includes a multi-layer printed circuit board. Furthermore the multiple output isolated power supply includes a planar transformer, which includes a plurality of secondary windings associated with different output channels, arranged on or in the multi-layer PCB. At least two output channels out of the output channels of the multiple output isolated power supply includes a rectifier and a voltage regulator or a current regulator.

A failure pattern obtaining method and apparatus are provided. The method includes that: a chip test result picture for a wafer is obtained, the chip test result picture being marked with a plurality of failure test points; a vector for every two points among all failure test points is calculated; a plurality of failure test points having a same vector are designated as a same group; a plurality of pending failure patterns are separated from each of groups; a failure pattern is obtained based on the plurality of the pending failure patterns.

A system, method, and device to test an electronic circuit are disclosed having a stage to supply a driving signal to a load comprising a pull-up switch and a pull-down switch and a pre-driver stage including pre-driver circuits. The electronic circuit including circuits for testing the pre-driver stage under the control of an automatic testing equipment (ATE) to operate a built-in self-test sequence including test commands for the pre-driver stage under the control of an external test signal issued by the ATE. The system includes a time measuring circuit to measure duration of signals at the output of the stage coupled to a pass-fail check circuit, and to evaluate if the duration of signals at the output of the stage to determine whether the output satisfies a pass criterion.

In accordance with at least one aspect of this disclosure, a controller for an aircraft electrical system includes, a software safe module. In embodiments, the software safe module can be configured to determine whether there was a sudden power failure upon controller initialization, and cause operation of the controller in a software safe mode if there was a sudden power failure such that manual intervention is required to leave the software safe mode to prevent repetitive power failure of the controller.

An automated test equipment (ATE) includes a test interface board assembly. The test interface board includes a socket configured to provide electrical couplings from the test interface board to a device under test (DUT). The socket is further configured to accept an active thermal interposer (ATI) device while the DUT is disposed in the socket. The socket includes a plurality of spring-loaded roller retention devices configured to retain one or more devices in the socket. The ATE further includes a Z-axis interface plate configured to open the plurality of spring-loaded roller retention devices to enable insertion of the DUT into the socket and an ATI placement plate configured to open the plurality of spring-loaded roller retention devices to enable insertion of the ATI device into the socket.

A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.

A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.