G01R31/2834

Inductance control system

An example polarity inverter includes multiple contactors, each of which includes switches that are controllable to configure a current path. Each of the multiple contactors includes contacts, which are interleaved such that first contacts to receive voltage having a first polarity alternate with second contacts to receive voltage having a second polarity, where the first polarity and the second polarity are different. The polarity inverter also includes a first conductive plate to connect electrically to each of the first contacts, and a second conductive plate to connect electrically to each of the second contacts. The first conductive plate and the second conductive plate are in parallel. A dielectric material is between the first conductive plate and the second conductive plate.

Defect localization in embedded memory

A system and method for defect localization in embedded memory are provided. Embodiments include a system including automated testing equipment (ATE) interfaced with a wafer probe including a diagnostic laser for stimulating a DUT with the diagnostic laser at a ROI. The ATE is configured to simultaneously perform a test run at a test location of the DUT with a test pattern during stimulation of the DUT. Failing compare vectors of a reference failure log of a defective device are stored. A first profile module is configured to generate a first 3D profile from each pixel of a reference image of the defective device. A second profile module is configured to generate a second 3D profile from each pixel of the ROI of the DUT. A cross-correlation module is configured to execute a pixel-by-pixel cross-correlation from the first and second 3D profiles and generate an intensity map corresponding to a level of correlation between the DUT and defective device.

Automotive Controller Testing
20230139159 · 2023-05-04 ·

Disclosed is a testing device for an automotive controller, which includes a plurality of Device Under Test (DUT) lines for connection to respective DUT lines in the automotive controller, and first and second multiplexers for selecting individual DUT lines. First and second measurement modules are connected to the multiplexers for measuring signal characteristics on the selected DUT lines. An interconnect circuit is operable for selectively connecting stimulation modules to the measurement modules for stimulating electrical signals on the selected DUT lines. A controller is provided to control the switching of the multiplexers and the interconnect circuit and for receiving the measured signal characteristics from the first and second measurement modules for testing the respective DUT lines in the automotive controller. Also disclosed are methods and software for controlling testing devices.

AUTOMATED SYSTEM FOR PRODUCING CONNECTORIZED EQUIPMENT AND MANAGING THE PRODUCTION THEREOF
20170370987 · 2017-12-28 ·

There is described a method for assembling a connectorized electrical equipment. A connectivity list required for the connectorized electrical equipment is provided, comprising an origin connector and its identifier, a destination electrical equipment subpart and its identifier thereof; and a list of connections between the origin connector and the destination electrical equipment subpart. By querying a database comprising a library of connectors, a construction plan is generated for the connectorized electrical equipment. The construction plan includes diagrams for assembly, images to assist the assembler, a list of material for managing inventory and instructions. An ATE can be connected to the connectorized electrical equipment to be assembled. Based on the construction plan, instructions are provided for a connection between the origin connector and the destination electrical equipment subpart. Connections can be made manually or using the ATE. All connections are registered in real time for progression tracking and instruction updates.

System and method of testing single DUT through multiple cores in parallel
11686768 · 2023-06-27 · ·

The present disclosure provides a method of testing a single device under test (DUT) through multiple cores in parallel, which includes steps as follows. The test quantity of the DUT is calculated; the test quantity of the DUT is evenly allocated to to a plurality of test cores, so as to control a period of testing the DUT through the test cores in parallel.

Systems and methods for circuit failure protection

In accordance with at least one aspect of this disclosure, a controller for an aircraft electrical system includes, a software safe module. In embodiments, the software safe module can be configured to determine whether there was a sudden power failure upon controller initialization, and cause operation of the controller in a software safe mode if there was a sudden power failure such that manual intervention is required to leave the software safe mode to prevent repetitive power failure of the controller.

Path loss compensation for comparator

A test system can receive a test signal from a device under test (DUI) via a first signal path. A comparator circuit can receive the test signal and, in response, generate an intermediate output signal based on a magnitude relationship between the test signal a comparator reference signal. A compensation circuit can generate a correction signal that is complementary to a portion of the received test signal, such as to correct for loading effects of the first signal path. The test system can include an output circuit configured to provide a corrected differential output signal that is based on a combination of the intermediate output signal and the correction signal.

METHOD AND SYSTEM FOR TESTING AN INTEGRATED CIRCUIT

A method is provided and includes several operations: testing multiple scan chains in multiple shift cycles to obtain multiple values; determining at least one fail chain in the scan chains and determining at least one fail shift cycle corresponding to at least one fail value in the values; mapping the at least one fail chain and the at least one fail shift cycle to the scan chains to identify the at least one fail flip flop; and identifying at least one fault site corresponding to the at least one fail flip flop.

Calibration board for calibrating signal delays of test channels in an automatic test equipment and timing calibration method thereof

A calibration board and a timing calibration method thereof are provided. The calibration board for calibrating signal delays of test channels in an automatic test equipment is pluggably disposed in the automatic test equipment and includes calibration groups, a first common node, and a switching module. Each calibration group includes a second common node and conductive pads electrically connecting to the second common node. Each conductive pad selectively and electrically connects to one test channel. The switching module electrically connects to the first common node and each second common node. When a first delay calibration procedure is performed, the connection between the first common node and each second common node is disabled. When a second delay calibration procedure is performed, the connection between the first common node and each second common node is built.

Automatic test system and method

An automatic test system and method are provided. The automatic test system includes at least one formation apparatus and a test fixture. The formation apparatus receives a first control command from a network and executes a test procedure according to the first control command. The test procedure includes a charging mode and a discharging mode. The test fixture is selectively coupled to the formation apparatus. During the test procedure, when the test fixture is coupled to the formation apparatus, the test fixture generates a first measurement result. The test fixture transmits the first measurement result to the formation apparatus via a wireless communication interface of the test fixture.