In a testing device, a method for implementing automatic RF port testing. The method includes attaching a device under test having a plurality of RF pins to a load board, dynamically tuning a plurality of RF ports of the load board to the plurality of RF pins, and automatically matching the plurality of RF ports to the plurality of RF pins with respect to impedance. The method further includes implementing an RF port testing process on the device under test.

An apparatus and method for testing equipment is provided. An analog test signal is received by an analog-to-digital converter. The test signal is converted to a digital test signal. The digital test signal is received by a digital processor. The digital test signal is processed and received by a digital memory and a digital-to-analog converter. The processed digital signal is converted to an analog test signal.

An I/O control circuit includes a plurality of IO cells including an input section for stimulating a plurality of (n) pins of a device under test (DUT) and an output section for processing data output by the pins. The input section of each cell includes a latched driver each including a driver input, a first driver output, a next state driver output, and a current source. The next state driver output and current source are for coupling to drive the pins, and the latched drivers are serially connected with the first driver output of an earlier IO cell connected to the driver input of a next IO cell. The output section of each cell includes an analog to digital converter (ADC) for coupling to the n pins, and a memory element coupled to an output of the ADC.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a test system comprises pre-qualifying test components, functional test components, a controller, a transceiver, and a switch. The pre-qualifying test components are configured to perform pre-qualifying testing on a device under test. The functional test components are configured to perform functional testing on the device under test. The controller is configured to direct selection between the pre-qualifying testing and functional testing. The transceiver is configured to transmit and receive signals to/from the device under test. The switch is configured to selectively couple the transceiver to the pre-qualifying test components and functional test components.

An inspection system for a semiconductor package includes an inspection apparatus that includes a stage on which the semiconductor package is loaded, and a computer coupled to the inspection apparatus. The semiconductor package may include a first semiconductor chip and a second semiconductor chip on the first semiconductor chip, the computer may provide first identification information about the first semiconductor chip and second identification information about the second semiconductor chip, and the computer may control the inspection apparatus to selectively perform a package test process on one of the first and second semiconductor chips, the one of the first and second semiconductor chips being identified as a good chip based on the first identification information and the second identification information.

A testing device of a data collecting chip (10) and control method thereof, and the testing device (10) includes: a data collecting module (200) for receiving multiple frames of sampling data sampling data collected by the data collecting chip; a storing module (300); a processing module (400) for calculating noise of a plurality of data sampling points to obtain a noise test result; a data transceiving module (500) for uploading the noise test result; and a control module (600). The testing device (10) only uploads the noise test result by calculating the noise of the plurality of data sampling points, so that the efficiency of a chip test is improved, the cost of the chip test is reduced, and the test reliability is ensured better.

Each of a plurality electronic circuit devices fixed to a structural component of a physical structure can be scanned a first time, using a radio frequency (RF) scanner to receive, from each of the plurality of electronic circuit devices, first data indicating a first measured electrical impedance of a respective conductor connected to the electronic circuit device and an identifier assigned to the electronic circuit device. For each of the plurality of electronic circuit devices, the first data indicating the first measured electrical impedance and the identifier assigned to the electronic circuit device can be stored to a first memory. The first data indicating the first measured electrical impedance and the identifier for each of the electronic devices can form a baseline measurement of the electronic circuit devices.

An automated circuit test system includes a magnetic sensor array configured to measure, at a plurality of locations, a magnetic field induced by a circuit under test. A circuit drive module can energize the circuit under test to induce the magnetic field. Optionally, the circuit drive module detects an electrical response from the circuit under test. Optionally, magnetic field data is combined with electrical response data prior to outputting the test result.

A testing device includes a connecting module and a processor electrically connected to the connecting module. The connecting module is electrically coupled with a plurality of communication devices under tests (DUTs) synchronously. The processor determines a schedule for the communication DUTs and tests the communication DUTs according to the schedule. A testing method is applied to the testing device to implement the operations.

A mixed signal testing system capable of testing differently configured units under test (UUT) includes a controller, a test station and an interface system that support multiple UUTs. The test station includes independent sets of channels configured to send signals to and receive signals from each UUT being tested and signal processing subsystems that direct stimulus signals to a respective set of channels and receive signals in response thereto. The signal processing subsystems enable simultaneous and independent directing of stimulus signals through the sets of channels to each UUT and reception of signals from each UUT in response to the stimulus signals. Received signals responsive to stimulus signals provided to a fully functional UUT (with and without induced faults) are used to assess presence or absence of faults in the UUT being tested which may be determined to include one or more faults or be fault-free, i.e., fully functional.