A display device including: a substrate including a display area and a peripheral area peripheral to the display area; a plurality of pads disposed in a pad area, wherein the pad area is disposed in the peripheral area and the pad area includes an integrated circuit (IC); and a first crack detecting line connected to a first pad and a second pad at a first node, and a third pad at a second node, wherein the first crack detecting line is disposed in the peripheral area between the first node and the second node.

Circuitry, systems, and methods for fault detection and reporting comprise a fault detection circuit configured to detect one or more fault conditions that cause a state change in a fault pin voltage representative of a transceiver failure. Once the state of the fault pin voltage changes, a transceiver input generates a fault detection code. In embodiments, in response to the transceiver input receiving a first signal, the fault detection code is shifted to a transceiver output that may communicate the fault detection code to a controller. Once the transceiver input receives a second signal, the fault pin voltage may be reset to clear the fault detection code before resuming operations, including detecting additional fault conditions as they arise.

The present invention concerns a method and device for monitoring the gate signal of a power semiconductor (SI), the gate signal of the power semiconductor (SI) being provided by a gate driver (12), generates an expected signal (VGexp) that corresponds to the signal outputted by the gate driver (12) when no deterioration of the gate driver (12) and/or of the power semiconductor (SI) and/or of a load linked to the power semiconductor (SI) exists, compares the expected signal (VGexp) and the signal (VGmeas) outputted by the gate driver (12), determines if a deterioration of the gate driver (12) and/or of the power semiconductor (SI) and/or of a load linked to the power semiconductor (SI) exists using the result of the comparing of the expected signal (VGexp) and the signal (VGmeas) outputted by the gate driver (12).

A system for estimating faulted area in an electric distribution system. The system includes a database storing input data, a fault detection module to estimate, based on the input data, if a new faulted area estimation process is required, a condition estimation module to estimate condition of metered protective devices, un-metered protective devices, and metered devices (PMDs), an upstream to downstream module to assess condition of each metered protective device, un-metered protective device, and metered device (PMD), starting from a feeder circuit breaker towards feeder downstream, to estimate a tripped protective device and a last metered device upstream of a fault, and a downstream to upstream module configured to assess outaged electric loads or elements towards network upstream to find the common interrupting protective device.

Systems and methods of testing the health of vehicular power devices are disclosed herein. A method may include producing operating points as a function of cycling current (I.sub.ds) and voltage drain to source (V.sub.ds) when a subject device is conducting current. The method may further include determining a mean of moving distribution to adapt a center of the moving distribution contrasted with a plurality of known healthy devices. The method may also include indicating an imminent fault in the subject device based upon a discontinuity among operating points above a threshold.

A method for designing a fault detection circuit includes an extraction step of selecting a fixed signal value based on an index, and extracting, by using the fixed signal value selected, one or some but not all of three-signal implication relationships.

Some embodiments described herein include a method to validate supply chains for electronic devices using side-channel information in a signature analysis. The method includes sending, to a target device, a first signal associated with a set of codes to be executed by the target device, and then receiving first side-channel information associated with the target device in response to the target device executing the set of codes. The method also includes determining second side-channel information associated with a simulated device in response to the set of codes. The method further includes comparing a discriminatory feature of the first side-channel information with a discriminatory feature of the second side-channel information to determine a characteristic of the target device based on a pre-determined characteristic of the simulated device. Finally, the method includes sending, to a user interface, a second signal associated with the characteristic of the target device.

Disclosed is a camera module inspector of rotating type distributing a load of processing test raw data. In an exemplary embodiment, the camera module inspector of rotating type includes a rotary index table including a plurality of socket units, a plurality of testers arranged around the rotary index table, a plurality of test control processors connected to correspond to the plurality of socket units, respectively, to be fixed on the rotary index table, a network connection unit establishing network connections with respect to the plurality of test control processors, a redundancy check processor processing the test raw data faster than the test control processor, connected to the network connection unit and data controller test raw data requiring a great deal of processing time out of the test raw data generated in the plurality of test control processors to be transmitted to the redundancy check processor through the network connection unit.

A gate driver circuit is provided that includes a high-side power transistor; a low-side power transistor coupled to the high-side power transistor, where an output voltage is generated at a load node coupled between the low-side power transistor and the high-side power transistor; a gate driver configured to receive a high-side control signal and a low-side control signal, drive the high-side power transistor based on the high-side control signal, and drive the low-side power transistor based on the low-side control signal; and a short circuit detection circuit configured to monitor for short circuit events at the high-side power transistor and at the low-side power transistor based on the high-side control signal, the low-side control signal, and the output voltage, and, generate a fault signal in response to detecting a short circuit event at either of the high-side power transistor or the low-side power transistor.

Apparatus detects an electrical fault in a primary tap having a plurality of distribution transformers each provided in a distribution circuit along a length of the primary tap, on a power distribution system. The apparatus includes a voltage monitor provided at each of the distribution circuits for monitoring a voltage in a corresponding distribution circuit, a controller in communication with each of the voltage monitor for receiving the voltage monitored and transmitted by the voltage monitors, and a fuse isolator configured to electrically connect the primary tap to a high voltage on the power distribution system and electrically disconnect the primary tap from the high voltage on power distribution system when activate. A fuse isolator actuator in communication with the controller is provided for activating the fuse isolator responsive to a control signal from the controller when a fault in the primary tap is detected by the controller, which determines that a fault exists in the primary tap based on the voltages monitored by the plurality of voltage monitors.