Circuitry, systems, and methods for fault detection and reporting comprise a fault detection circuit configured to detect one or more fault conditions that cause a state change in a fault pin voltage representative of a transceiver failure. Once the state of the fault pin voltage changes, a transceiver input generates a fault detection code. In embodiments, in response to the transceiver input receiving a first signal, the fault detection code is shifted to a transceiver output that may communicate the fault detection code to a controller. Once the transceiver input receives a second signal, the fault pin voltage may be reset to clear the fault detection code before resuming operations, including detecting additional fault conditions as they arise.

A thermal abnormality detection system includes: a first heat dissipation system having a first temperature sensor for measuring an actual temperature of the first heat dissipation system; a second heat dissipation system having a second temperature sensor for measuring an actual temperature of the second heat dissipation system. Assuming that a difference between the actual temperature of the first heat dissipation system and an upper limit temperature of the first heat dissipation system is d1, and a difference between the actual temperature of the second heat dissipation system and an upper limit temperature of the second heat dissipation system is d2, when a value of d1−d2 is greater than an error threshold value Error1_level, the first heat dissipation system is determined to be abnormal, and when the value of d1−d2 is less than an error threshold value Error2_level, the second heat dissipation system is determined to be abnormal.

A system and associated method determines the characteristics of an electric network including distance to a fault through the use of a power divider and a measuring device that measures a quantity from which voltage magnitude can be determined. The measuring device may be a power detector. The power detector may include a power meter to measure voltage and/or a power sensor to measure amplitude. Then, the results from the power detector are used in conjunction with a Hilbert transform to estimate the phase associated with at least two voltage magnitudes when a combined signal is a minimum phase signal.

A method of testing a device comprises receiving signals from a device under test (DUT) and computing an eye diagram using the signals received from the DUT. The method also comprises comparing an eye height and an eye width of the eye diagram to a predetermined values of a threshold eye height and a threshold eye width. Further, responsive to a determination of the eye height and the eye width exceeding the predetermined values of the threshold eye height and the threshold eye width, flagging the DUT as passing.

There are provided a detection method and detection apparatus of an operating state of a circuit. The method includes: forming a neural network that acquires a state category of a circuit to be detected; measuring electrical characteristic parameters of at least one node in the circuit to be detected; inputting the measured electrical characteristic parameters of at least one node to the neural network, and obtaining the state category of the circuit to be detected through the neural network.

A method for detecting fault direction of transmission line of an AC power system and control system using the same. The method includes: sampling current values and voltage values of three phases at one end of the transmission line for a series of time points; for each of the series of time points, computing instantaneous symmetrical voltage components of the three phases based on the voltage value samples for the respective one of the series of time points; for each of the series of time points, computing instantaneous symmetrical current components of the three phases based on the current value samples for the respective one of the series of time points; for at least two of the series of time points, calculating energy directional elements each based on the respective ones of the computed instantaneous symmetrical voltage components and the respective ones of the computed instantaneous symmetrical current components; identifying the fault direction in consideration of the calculated energy directional elements; and generating a fault direction signal indicating the identified fault direction. Simulation results show the graph of the energy directional element calculated based on instantaneous symmetrical voltage components and instantaneous symmetrical current components exhibits distinctive characteristics either for forward or reverse fault. In consideration of such difference, by calculating the energy directional element at each sampling time point, the fault direction information may be identified accurately.

Apparatus and associated methods relate to a functional self-test, including (1) generation of an excitation signal, (2) applying the excitation signal to a unit under test (UUT), the excitation signal including a cyclical signal for a first interval and substantially zero signal for a second interval, (3) determining frequency content of a UUT response signal, and (4) generating a fail result in response to the frequency content below a predetermined threshold. In an illustrative example, the UUT may be a piezoelectric element (PE). The UUT response signal may be processed by a filter, for example. A portion of the filtered UUT response signal, responding to the second interval of the excitation signal, may be analyzed by a fast Fourier transform module (FFTm), for example. In various implementations, the functional self-test may advantageously determine the health of a piezoelectric gas sensing element, periodically, in a field-deployed implementation.

A test pattern generating method for generating a test pattern for a circuit under test. The test pattern generating method comprises: (a) computing a plurality of signal delay values which a plurality of cells have due to different defects; (b) comparing the signal delay values and signal path delay information of a target circuit to generate a fault model; and (c) generate at least one test pattern according to the fault model.

An apparatus for detecting difference in operating characteristics of a main circuit by using a replica circuit is presented. In one exemplary case, a sensed difference in operating characteristics of the two circuits is used to drive a tuning control loop to minimize the sensed difference. In another exemplary case, several replica circuits of the main circuit are used, where each is isolated from one or more operating variables that affect the operating characteristic of the main circuit. Each replica circuit can be used for sensing a different operating characteristic, or, two replica circuits can be combined to sense a same operating characteristic.

An inspection method according to an embodiment is an inspection method of performing laser marking on a semiconductor device (D) including a substrate (SiE) and a metal layer (ME) formed on the substrate (SiE), and the inspection method includes specifying a fault point (fp) in the semiconductor device (D) by inspecting the semiconductor device (D), and irradiating the semiconductor device (D) with laser light having a wavelength that is transmitted through the substrate (SiE) from the substrate (SiE) side so that a marking is formed at least at a boundary between the substrate (SiE) and the metal layer (ME) on the basis of the fault point (fp).