A method includes placing a semiconductor device package in a test handler, the semiconductor device package having leads of a first portion of a package substrate extending from a mold compound and leads of a second portion isolated from the first portion extending from the mold compound; contacting the first portion with a first and a second conductive slug; contacting the second portion with a third and a fourth conductive slug; contacting a first surface of the mold compound with a first plunger having a conductive plate and an insulating tip; contacting an opposite second surface of the mold compound with a second plunger having a conductive plate and an insulating tip; and placing a high voltage on the first conductive slug while placing approximately half the high voltage on the conductive plate of the first plunger, and placing a ground voltage on the third conductive slug.

The degree of freedom of an abnormality detection target location in a solid-state imaging device in which a plurality of substrates are joined is improved. A semiconductor device includes a connection line and a detection circuit. A plurality of semiconductor substrates are joined in the semiconductor device. Then, in the semiconductor device, the connection line is wired across the plurality of semiconductor substrates. The detection circuit detects the presence or absence of an abnormality in a joint surface of the plurality of semiconductor substrates based on an energization state of the connection line when enable has been set by a predetermined control signal.

A semiconductor system, a semiconductor device, a through-silicon via (TSV) test method, and a method of manufacturing a semiconductor device are provided. The semiconductor system includes a semiconductor device including a buffer die and first to L-th (where L is an integer greater than or equal to 2) stack dies stacked on the buffer die and communicating with the buffer die through N (where N is a positive integer) TSVs; and a TSV test device that measures each of voltages at one end and voltages at another end on the N TSVs according to a clock signal, compares each of the voltages at the one end and the voltages at the other end with a reference voltage, and determines whether each of the N TSVs has a plurality of TSV defect types according to comparison results.

Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.

A circuit includes a gain stage, first and second amplifiers, and a comparison circuit. The gain stage has an input and an output. The first amplifier has an input and an output. The input of the first amplifier is coupled to the input of the gain stage. The second amplifier has an input and an output. The input of the second amplifier is coupled to the output of the gain stage. The comparison circuit is coupled to the outputs of the first and second amplifiers. The comparison circuit is configured to compare signals on the outputs of the first and second amplifiers and to generate a fault flag signal responsive to the output signal from the first amplifier being different than the output signal from the second amplifier.

The present disclosure provides a test apparatus and a jumper thereof. The test apparatus includes a base board and the jumper. The base board has a first slot and a second slot. The first slot has a plurality of electrical contacts, and is configured to receive a plurality of pins of a device under test. The jumper is inserted into the second slot. The jumper includes a body and a plurality of first circuits. The first circuits are disposed on the body and electrically connect the electrical contacts of the first slot to a plurality of pins of a tester.

A latchup immune microcontroller system with a power supply and a filter designed to eliminate external risks of triggering a latchup of a microcontroller caused by the power supply; a clock circuit with a clock frequency and a layout for eliminating external risks of triggering a latchup of the microcontroller caused by a high-frequency clock signal; a reset circuit that uses an optical triggering mechanism acting as a common power supply and an isolated power supply, the power detection circuit and a discharge circuit react in chain in time, avoid risks of triggering latchups of the microcontroller caused by reset signals; an interrupt with a high priority level and the discharge circuit react in chain in time to enhance data security, and output terminals are turned off in sequence to remove external causes of latchup. An application method of an I/O port to eliminate triggers of latchup of the microcontroller.

The present application provides a structure and method for online detection of a metal via open circuit, a contact layer is on the substrate, a first metal layer is on the contact layer, a first metal via layer is on the first metal layer, a second metal via layer is on the first metal via layer metal layer, the contact layer comprises a plurality of contacts, the plurality of contacts are connected to the first metal layer, the first metal via layer comprises a plurality of first vias, the plurality of first vias are filled with metal; detecting by means of an E-beam technology. A problem in the process can be found in advance, so as to solve the problem in time and thus stop losses as soon as possible.

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

An IC includes a plurality of pads at a top surface of a semiconductor wafer, an amplifier configured to receive a first AC signal at an input terminal, and output a second AC signal at an output terminal, a first detection circuit coupled to the input terminal and configured to output a first DC voltage to a first pad of the plurality of pads responsive to the first AC signal, and a second detection circuit coupled to the output terminal and configured to output a second DC voltage to a second pad of the plurality of pads responsive to the second AC signal.