Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.

A semiconductor module including a semiconductor element which is bonded to a wiring pattern part and connects or disconnects two main electrode terminals to or from each other according to a drive signal applied to a gate electrode terminal, includes a deterioration detecting circuit configured to use one main electrode terminal of the two main electrode terminals of the semiconductor element with an applied DC voltage, as a reference potential, and detect deterioration of a joining part of the semiconductor element on the basis of a gate voltage which is the voltage between the one main electrode terminal and the gate electrode terminal and an inter-main-electrode voltage which is the voltage between the one main electrode terminal and the other main electrode terminal, and outputs an alarm signal.

A test structure and method to detect open circuits due to electromigration or burn-out in test wires and inter-level vias. Electromigration occurs when current flows through circuit wires leading to a circuit interruption within the wire. The test structure is a passive test wire arranged in one of several configurations within the circuit of a computer chip. The dimensions and resistances of test wires can vary according to the test structure configuration. Each test wire is measured for an electrical discontinuity after the computer chip is powered-on. If a wiring interruption is detected, it is concluded that the chip had been powered-on before.

Packaged integrated circuit devices include an oscillator circuit having a resonator (e.g., quartz crystal, MEMs, etc.) associated therewith, which is configured to generate a periodic reference signal. A built-in self-test (BIST) circuit is provided, which is selectively electrically coupled to first and second terminals of the resonator during an operation by the BIST circuit to test at least one performance characteristic of the resonator, such as at least one failure mode. These test operations may occur during a built-in self-test time interval when the oscillator circuit is at least partially disabled. In this manner, built-in self-test circuitry may be utilized to provide an efficient means of testing a resonating element/structure using circuitry that is integrated within an oscillator chip and within a wafer-level chip-scale package (WLCSP) containing the resonator.

Embodiments of the disclosure are drawn to apparatuses and methods for testing through silicon vias (TSVs) which may be used, for example, to couple layers of a semiconductor memory device. The TSVs and/or the die around the TSVs may require testing. A switch circuit may be used to selectively couple one or more test circuits to an amplifier. The test circuits may generate a voltage that is related to one or more parameters of the TSV being tested. The amplifier may amplify the voltage, which may be used to determine if the TSV passes the particular test determined by the test circuit selected by the switch circuit. The switch circuit and/or other components of the test circuits may be controlled by control signals to determine the operation of a particular test.

A semiconductor device includes: a plurality of semiconductor chips; and a connecting portion that connects a plurality of terminals formed on the plurality of semiconductor chips, wherein the plurality of terminals of the plurality of semiconductor chips belong to one of first group or second group, an interval between one of first terminals belonging to the first group and one of second terminals belonging to the second group is a predetermined interval, the one of the second terminals being adjacent to the one of the first terminal, the first terminals are arranged at an interval larger than the predetermined interval, and each of the plurality of semiconductor chips includes a selecting portion that selects a signal transmitting terminal among the plurality of terminals, per each of the groups.

A simultaneous electrical testing device for TSV interconnection elements passing through a substrate and including one end connected to an integrated testing circuit and another end to a removable connection mechanism assembled to the substrate through an anisotropic conductive glue.

A lidar sensor assembly includes a detector array having a plurality of photodetectors. An integrated circuit is bonded to the detector array via a plurality of connection bumps. A reference trace is defined by conductive material on at least one of the integrated circuit and the detector array. A test trace is defined by conductive material on the detector array, at least two of the connection bumps, and conductive material on the integrated circuit. A resistance measuring device is configured to independently measure a reference resistance along the reference trace and a test resistance along the test trace. The assembly also includes a processor in communication with the resistance measuring device. The processor is configured to receive the reference resistance and the test resistance, subtract the reference resistance from the test resistance to produce a bond resistance, and compare the bond resistance to a predetermined resistance value.

The disclosure relates to an integrated circuit and associated method and packaged integrated circuit. The integrated circuit comprises a first pad; a second pad; an active element having a node that is capacitively coupled to the first and second pads; a voltage or current source connected to the first pad; and a detection module connected to the second pad and configured to determine an electrical continuity between the second pad and the first pad.

A deskew fixture includes first and second deskew probe points for contacting first and second probes, respectively, during deskew calibration, a signal generating circuit for generating a calibration signal provided to the first and second deskew probe points, and a feedback loop for automatically self-calibrating the deskew fixture. The feedback loop includes first and second analog to digital converters (ADCs) for digitizing the calibration signal at the first and second deskew probe points while contacting the first and second probes, respectively, to provide first and second digitized calibration signals, and a processing unit programmed to determine inherent skew of the deskew fixture between the first and second skew probe points using the first and second digitized calibration signals, and to provide the determined inherent skew to a test instrument for use in the deskew calibration of the first and second probes.