A method and system for re-using the electrical energy of an electronic component under test. The method and system includes combining a first direct current voltage output of an electronic component under test with a second direct current voltage of a device. The combined first direct current voltage and second direct current voltage are regulated to create a power. The power functions a system application. At least one metric of the electronic component under test is monitored.

A method for characterizing an integrated circuit that selecting at least two devices from an integrated circuit for measuring light emission, wherein each of the at least two devices have experienced a different level of stress, applying power to the integrated circuit, and measuring the light emission from the at least two devices. The method also includes comparing the light emission that is measured from the at least two devices, wherein a difference between the light emission that is measured from the at least two devices greater than a predetermined ratio indicates that at least one of the devices from the at least two devices has a below specification performance.

A test board and a test apparatus having the same are disclosed. The test board includes a base plate including a connector and a plurality of mounting areas in a matrix shape having a mounting row in a first direction and a mounting column in a second direction, a plurality of test units arranged on the mounting areas of the base plate and a test object is mounted in each of the mounting areas, and a fluid supplier disposed on the base plate and supplying a test fluid to each of the test units having a test temperature and a supplementary fluid to the test object to reduce a temperature difference between an actual temperature of the test object and the test temperature such that the actual temperature of the test objects is substantially below the test temperature.

Systems and methods for semiconductor design evaluation. IC layout information of a circuit design is received, and the circuit design is decomposed into smaller circuit pieces. Each circuit piece has IC layout information and a netlist. For each circuit piece, a set of strike models is selected based on the layout information and the net-list of the circuit piece and received radiation environment information. Each strike model has circuit components with voltage values corresponding to a respective particle strike. For each selected strike model of a circuit piece: a radiation susceptibility metric is determined by comparing functional results of simulation of the of the strike model with functional results of simulation of the circuit piece. For each circuit piece, a radiation susceptibility metric is determined based on the radiation susceptibility metrics generated for each selected strike model of the circuit piece.

A semiconductor device includes a temperature sensor, a scan control circuit which generates scan chain selection information in accordance with a measurement result of the temperature sensor, a clock control circuit which generates one or more scan chain clock signals based on an external clock signal and the scan chain selection information, a pattern generation circuit which generates a test pattern, and a logic circuit which includes a plurality of scan chains and which receives the scan chain clock signals and the test pattern. The clock control circuit generates the scan chain clock signal in association with each scan chain. During a burn-in test, the logic circuit captures the test pattern into the scan chain associated with the scan chain clock signal.

Systems and methods for semiconductor design evaluation. IC layout information of a circuit design is received, and the circuit design is decomposed into smaller circuit pieces. Each circuit piece has IC layout information and a netlist. For each circuit piece, a set of strike models is selected based on the layout information and the net-list of the circuit piece and received radiation environment information. Each strike model has circuit components with voltage values corresponding to a respective particle strike. For each selected strike model of a circuit piece: a radiation susceptibility metric is determined by comparing functional results of simulation of the of the strike model with functional results of simulation of the circuit piece. For each circuit piece, a radiation susceptibility metric is determined based on the radiation susceptibility metrics generated for each selected strike model of the circuit piece.

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

Techniques are described for systematically and efficiently converting or otherwise accelerating latent defects in semiconductor devices into gross defects by applying appropriate defect acceleration stimulus to the semiconductor devices. Techniques are also described for evaluating test patterns to determine their effectiveness in accelerating the transition of latent defects to gross defects. This evaluation effectively allows various stress patterns to be graded or ranked, so that an optimal or high-confidence one can be selected. Such grading of possible stress patterns increases the probability that a given latent defect will escalate or otherwise manifest.