To include in a device a controller to control operation of the device in a normal-operation mode and in a test mode for performing one or more tests including an accelerated aging test, a temperature sensor to measure operating temperature of the device, and an overheat protection circuit to prevent overheating of the memory device during the test mode. With this overheat protection circuit, a device may undergo an efficient and reliable accelerated aging test with reduced or non-existent, possibility of suffering an overheat damage.

To provide a voltage regulator capable of switching a voltage of an output terminal from an internal voltage to an external voltage while suppressing an increase in circuit scale. The voltage regulator includes a voltage output circuit configured to generate a constant internal voltage lower than an external voltage applied to an input terminal from the external voltage and supplying the constant internal voltage to an output terminal, a temperature sensing circuit configured to decrease an output voltage of an output node thereof according to a rise in temperature, an overheat detection circuit connected to the output node of the temperature sensing circuit and a test terminal, and a voltage detection circuit connected to the output node of the temperature sensing circuit and the test terminal.

A test device is provided. An output terminal of an operational amplifier is coupled to a device under test. A current replication circuit copies a current flowing through a charging circuit and a discharge circuit according to voltages of control terminals of the charging circuit and the discharge circuit in the operational amplifier and outputs a test result signal.

Systems and methods for semiconductor design evaluation. IC layout information of a circuit design is received, and the circuit design is decomposed into smaller circuit pieces. Each circuit piece has IC layout information and a netlist. For each circuit piece, a set of strike models is selected based on the layout information and the net-list of the circuit piece and received radiation environment information. Each strike model has circuit components with voltage values corresponding to a respective particle strike. For each selected strike model of a circuit piece: a radiation susceptibility metric is determined by comparing functional results of simulation of the of the strike model with functional results of simulation of the circuit piece. For each circuit piece, a radiation susceptibility metric is determined based on the radiation susceptibility metrics generated for each selected strike model of the circuit piece.

An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate, an electrical connection structure extending upwardly from an upper surface of the substrate by a first height, and a contact pad electrically disposed on the upper surface of the substrate. The contact pad has a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height. The semiconductor device structure further includes a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad.

A method and system for re-using the electrical energy of an electronic component under test. The method and system includes combining a first direct current voltage output of an electronic component under test with a second direct current voltage of a device. The combined first direct current voltage and second direct current voltage are regulated to create a power. The power functions a system application. At least one metric of the electronic component under test is monitored.

A semiconductor device may be provided. The semiconductor device may include a first oscillation signal generation circuit for generating a first oscillation signal. The semiconductor device may include a second oscillation signal generation circuit for generating a second oscillation signal. The second oscillation signal generation circuit may be provided with a test voltage. The test voltage may be generated based on a burn-in test signal.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate, an electrical connection structure extending upwardly from an upper surface of the substrate by a first height, and a contact pad electrically disposed on the upper surface of the substrate. The contact pad has a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height. The semiconductor device structure further includes a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad.

A method and system for re-using the electrical energy of an electronic component under test. The method and system includes combining a first direct current voltage output of an electronic component under test with a second direct current voltage of a device. The combined first direct current voltage and second direct current voltage are regulated to create a power. The power functions a system application. At least one metric of the electronic component under test is monitored.