Various implementations described herein are related to a method for constructing integrated circuitry and identifying input signal paths, internal signal paths and output signal paths associated with the integrated circuitry. The method may include generating a timing table for slew-load characterization of the input signal paths, the internal signal paths and the output signal paths. The method may include simulating corner points for the timing table, building diagonal points for the timing table based on the simulated corner points, and building remaining points for the timing table based on the simulated corner points and the diagonal points.

One specific example involves an integrated circuit that has application logic circuitry which includes flip-flop circuits susceptible to degradations of setup and hold times relative to specified minimum setup and hold times for signals to be processed by the respective flip-flop circuits. In a method carried out by the integrated circuit, timing-based logic states of the flip-flop circuits are controlled, based on at least one transition-scan pattern processed by the flip-flop circuits as part of the application logic circuitry; and respective logic states are set for those flip-flops, which due to degradations of the actual setup and hold times do not satisfy anymore the originally specified minimum setup and hold times.

A computer system may determine a first set of output values for a set of test paths at a first time. Each output value may correspond to a test path in the set of test paths. The computer system may then determine a second set of output values at a second time. Each output value in the second set of output values may have an associated output value in the first set of output values. The computer system may then determine whether degradation of the semiconductor chip has occurred by comparing the first set of output values to the second set of output values.

There is provided a semiconductor inspection device capable of detecting an abnormality with high sensitivity in a failure analysis of a fine-structured device. The semiconductor inspection device includes: a sample stage 6 on which a sample is placed; an electron optical system 1 configured to radiate an electron beam to the sample; a measurement probe 3 configured to come into contact with the sample; a measurement device 8 configured to measure an output from the measurement probe; and an information processing device 9 configured to acquire a measurement value of the output from the measurement probe in response to radiation of the electron beam to the sample. The information processing device sets a timing to start the radiation of the electron beam to the sample and a timing to freeze the radiation of the electron beam, a first measurement period in which the measurement device measures the output from the measurement probe in a state where the electron beam is radiated to the sample, and a second measurement period in which the measurement device measures the output from the measurement probe after the radiation of the electron beam is frozen, and obtains the measurement value of the output from the measurement probe in response to the radiation of the electron beam to the sample from a difference between a first measurement value measured in the first measurement period and a second measurement value measured in the second measurement period.

A chip health monitor includes a processor configured to operate as a state machine based on instructions stored in a storage device. The state machine is configured to exercise a signal path in a chip in response to a condition and determine presence of an error in the signal path based on results from the exercise. The state machine is configured to compensate for the error by changing at least one operational parameter of the chip.

A method for predicting an operation parameter of an integrated circuit includes the following steps. A plurality of cells used by the integrated circuit are provided. A voltage-frequency sweep test is performed on each of cells through a test model to generate a plurality of parameters, wherein the parameters correspond to a voltage value. A lookup table is established according to the parameters. A timing signoff corresponding to the integrated circuit is obtained. A timing analysis is performed on a plurality of timing paths of the integrated circuit according to the timing signoff and the parameters of the lookup table to obtain a critical timing path, and the operation parameter of the integrated circuit is predicted according to the critical timing path.

A TSV detecting circuit, TSV detecting methods, and an integrated circuit thereof are disclosed by the present disclosure. The TSV detecting circuit includes a first detecting module includes: a first comparison unit; a first input unit, for transmitting an input signal to a first input of the first comparison unit controlled by a first clock signal; a first switching unit for transmitting a signal of a first node to a second input of the first comparison unit controlled by a first detection control signal, the first node coupled to a first terminal of the TSV; and a second detecting module includes: a second input unit for transmitting the input signal to a second node controlled by a second clock signal; a second switching unit for transmitting a signal of the second node to a second terminal of the TSV controlled a second detection control signal.

An integrated circuit is provided. The integrated circuit includes a plurality of skitter circuits and a multiplexer that provides the waveform to the plurality of skitter circuits. The plurality of skitter circuits includes at least a first skitter circuit and a second skitter circuit. The first and second skitter circuits are arranged in parallel with respect to an output of the multiplexer. The first skitter circuit can include a first data path and a plurality of first inverters on that first data path. Further, the second skitter circuit can include a second data path, a plurality of second inverters on the second data path, and a delay element connected in series with an input of an initial inverter of the plurality of the second inverters on the second data path.

Performance measuring circuitry, for determining relative operational performance attributes of different types of a class of semiconductor component disposed on a semiconductor die, includes a first oscillator circuit including a plurality of first circuit element modules having a first circuit topology. The first oscillator circuit provides a first performance indication indicative of a collective performance attribute of all types of components in the class. A second oscillator circuit separate from the first oscillator circuit includes a plurality of second circuit element modules having a second circuit topology, and provides a second performance indication responsive to different contributions from different types of components in the class. A comparison circuit receives outputs of the first and second oscillator circuits and determines the relative performance characteristic of the different types of components. Dice may be binned according to performance, for use in assembly of operational circuits with different performance characteristics.

A method and apparatus for determining jitter, a storage medium and an electronic device are disclosed. The method for determining jitter includes: determining a plurality of measurement time points for an output signal from an integrated circuit (IC); identifying one or more jitter points from the plurality of measurement time points by comparing the output signal with a predetermined signal at the plurality of measurement time points; and determining a jitter of the output signal of the IC based on the one or more jitter points. The jitter of the output signal of an IC chip can be determined without relying on any other additional equipment.