A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

A chip health monitor includes a processor configured to operate as a state machine based on instructions stored in a storage device. The state machine is configured to exercise a signal path in a chip in response to a condition and determine presence of an error in the signal path based on results from the exercise. The state machine is configured to compensate for the error by changing at least one operational parameter of the chip.

A testing device includes a switch, a sensing circuit, and a control circuit. The switch is coupled to a power supply circuit, and the power supply circuit is configured to output a supply voltage to a device under-test via the switch. The sensing circuit is coupled to the device under-test, and the sensing circuit is configured to receive an input voltage from the device under-test and to output a sensing signal according to the input voltage. The control circuit is coupled to the sensing circuit, the power supply circuit, and the switch. The control circuit is configured to control the power supply circuit to stop outputting the supply voltage at a first time and to turn off the switch at a second time according to the sensing signal.

A test meter and related method for monitoring the condition of a backlight battery of the meter in which the meter includes a housing, controller, display with backlight and a battery monitoring circuit. An off-time of the meter is measured and compared to a predetermined recovery time of the backlight battery. If the off-time of the meter is greater than the predetermined recovery time of the backlight battery, a voltage of the backlight battery is measured at a predetermined time after energizing the backlight and compared to a first predetermined voltage in excess of a threshold voltage of the backlight battery. If the measured voltage is less than the first predetermined voltage, the measured voltage is compared to a second predetermined voltage between the first predetermined voltage and the threshold voltage. A battery depletion warning is displayed if the measured voltage is less than the second predetermined voltage.

A duty cycle measurement circuit obtains differential duty cycle measurements corresponding to the duty cycle of a signal at two or more different locations along a propagation path. The differential duty cycle measurements may include measurements of an input duty cycle and measurements of an output duty cycle. The duty cycle measurements may be acquired by use of duty-cycle-to-voltage converter circuitry. The duty cycle measurements may be used to determine a measure of the duty cycle deterioration of the propagation path, and an adjustment factor to compensate for the measured duty cycle deterioration.

An integrated circuit includes a plurality of external terminal circuits, each having an external terminal. The integrated circuit includes a wakeup detector including a plurality of inputs. Each input of the plurality of inputs is coupled to an external terminal circuit. The wakeup detector generates an output signal indicative of an external terminal of the plurality of external terminal circuits being placed at a wakeup voltage. The integrated circuit includes a trigger generation circuit having a plurality of outputs in which each output is coupled to an external terminal circuit to generate a wake-up voltage at an external terminal of the external terminal circuit by coupling the external terminal to a power supply terminal of the integrated circuit to generate an indication of the external terminal being at the wakeup voltage at the wakeup detector when at least a portion of the integrated circuit is in a low power mode.

Aspects of the present disclosure provide techniques for predicting a failure of an integrated circuit, which may include receiving first aging sensor data during an idle state of the integrated circuit; determining a voltage compensation value based on the first aging sensor data; comparing a new voltage value based on the voltage compensation value to a threshold operating voltage; determining the new operating voltage value exceeds the threshold operating voltage; determining a warning state for the integrated circuit; receiving second aging sensor data during the idle state of the integrated circuit; receiving stored aging sensor data from an aging sensor data repository; comparing the second aging sensor data to the stored aging sensor data; determining that the second aging sensor data is inconsistent with the stored aging sensor data; and determining a danger state for the integrated circuit.

A memory controller instantiated on a semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The memory controller further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

A test apparatus for testing electrical parameters of a target chip, the apparatus including: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

An address register includes a plurality of edge-triggered flip-flop registers having an input D, an input R, an input CK, and an output Q; a counter logic; a shifter logic; a multiplexer; input ports including a reset signal RST, a clock signal CLK, a shift enable signal SE, a shift data input signal SI; an output port including address signals ADDR. D is coupled to a data output of the multiplexer; R is coupled to a reset (RST) pad; CK is coupled to a clock (CLK) pad; Q is coupled to an address (ADDR) pad; an input of the counter logic is coupled to ADDR; an input of the shifter logic is coupled to ADDR and the shift data input signal SI; an input of the multiplexer is coupled to SE, an output of the counter logic, and an output of the shifter logic.