Signal delay, etc. in a signal path from an electrode pad to a functional block is reduced. An input-output block A and an input-output block B are connected to electrode pads. A functional block A is connected to the electrode pads via the input-output block A. A functional block B is connected to the electrode pads via the input-output block B. The functional block A and the functional block B are arranged at positions opposed to each other so as to sandwich the input-output block A and the input-output block B.

A test socket includes: a first body including a fixing portion configured to receive a sample having a plurality of test terminals; a second body facing the first body and coupled with the first body such that the second body rotates relative to the first body about a hinge pin; a test board provided on the second body and configured to test the sample, wherein the test board has a plurality of first openings provided therein; and a plurality of interface pins penetrating through the first openings, wherein each of the plurality of interface pins includes a contact pin and a spring, wherein the contact pin is provided in a first end portion of each of the plurality of interface pin and is configured to come into contact with a test terminal of the plurality of test terminals, and the spring elastically supports the contact pin.

Embodiments of the invention provide for integrated circuits for testing one or more transistors for process variation effects. According to an embodiment, the integrated circuit can include: a plurality of ring oscillator macro circuits, wherein each ring oscillator macro circuit includes two ring oscillators, a first multiplexer, and a first divide-by-two circuit; a multiplexer stage; a divide-by-two circuit stage; a second multiplexer; a second divide-by-two circuit; and frequency measurement circuit. According to another embodiment, the integrated circuit can include: a first shift register including a plurality of devices-under-test; a second shift register including a plurality of static latches; a first multiplexer configured to receive outputs from each of the plurality of DUTs; a second multiplexer configured to receive outputs from each of the plurality of static latches; and a comparator configured to compare an output from the first multiplexer with an output from the second multiplexer.

A semiconductor device may include: first to n-th through-electrodes; first to n-th through-electrode driving circuits suitable for charging the first to n-th through-electrodes to a first voltage level, or discharging the first to n-th through-electrodes to a second voltage level; and first to n-th error detection circuits, each suitable for storing the first voltage level or the second voltage level of a corresponding through-electrode of the first to n-th through-electrodes as a down-detection signal and an up-detection signal, and outputting a corresponding error detection signal of first to n-th error detection signals by sequentially masking the down-detection signal and the up-detection signal.

Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

A semiconductor device includes a semiconductor substrate having a main surface over which a plurality of die pads and at least one alignment pad for optical process control for semiconductor wafer probing are arranged. The alignment pad has a hardness smaller than a hardness of the plurality of die pads.

Disclosed herein are apparatuses and methods for mitigating sticking of units-under-test (UUTs). For example, in some embodiments, a probe card may include a probe landing pad, a guide plate having a hole therein, and a pushing mechanism. The pushing mechanism may include a pusher needle and a pusher needle support, the pusher needle support may be between the probe landing pad and the guide plate, and the pusher needle support may be controllable to cause the pusher needle to extend and retract through the hole in the guide plate.

The present invention provides a method of generating dummy patterns and calibration kits, including steps of generating devices-under-test (DUTs) using a point of said chip window layer as reference point in a unit cell, generating calibration kits corresponding to the DUTs using the point as reference point in corresponding unit cells, generating DUT dummy patterns for each DUTs individually in the unit cell, copying the DUT dummy patterns in the unit cell to the corresponding calibration kits in the corresponding unit cells using the point as reference point, and merging all of the unit cell and corresponding unit cells into a final chip layout.

A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.

Provided are a display panel and a display device. A peripheral circuit region is provided with a first pad group, a second pad group and multiple first signal lines. The first pad group includes a plurality of first pads, and the second pad group includes a plurality of second pads. An end of each of the plurality of the first signal lines adjacent to the first side is electrically connected to a respective one of the plurality of first pads, and an end of each of the plurality of the first signal lines adjacent to the second side is electrically connected to a respective one of the plurality of second pads.