The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.

A test socket assembly includes a contactor body having one or more compliant interconnects, and a socket opening sized and configured to receive a device under test therein. The test socket assembly further includes a lead frame assembly disposed within the contactor body and electrically coupled with the one or more compliant interconnects, and one or more antennas at least partially disposed within the contactor body, the one or more antennas configured to directly and wirelessly communicate to the device under test when the device is disposed within the socket opening.

An integrated circuit testing assembly, comprising a slab having a slab axis, and a first electrode and second electrode affixed relative to the slab. The first electrode has a first major axis parallel to the slab axis, is coupled to receive a first voltage for coupling to a first set of pins on an integrated circuit, and includes a first surface area facing the slab axis, wherein the first surface area does not include a surface discontinuity. The second electrode has a second major axis parallel to the slab axis, is coupled to receive a second voltage for coupling to second first set of pins on an integrated circuit, and includes a second surface area facing the slab axis, wherein the second surface area does not include a surface discontinuity.

A probe test card includes a substrate, a plurality of test needles, and a fixing layer. The substrate includes a first surface at which a trench is formed, and a second surface opposite to the first surface. The plurality of test needles is arranged in the trench. Each test needle includes a first end and a second end being opposite to the first end. The fixing layer is filled in the trench to fix the plurality of test needles in the trench, and a thickness of the fixing layer is same with a depth of the trench. The fixing layer comprises a ceramic powder. The first end of the test needle is non-removably fixed in the trench by the fixing layer and the second end of the test needle protrudes from the trench of the substrate to test a device under test (DUT).

A wafer inspection method and inspection apparatus that perform a voltage inspection of a die on a wafer by a probe module. The probe module includes a processing module, a first probe coupled to a first electrode point of the die, and a second probe coupled to a second electrode point of the die. The first probe is coupled to the processing module, and the second probe is grounded. The processing module provides the die with a driving current through the first probe, and obtains an inspection voltage corresponding to the die. The processing module generates an inspection result of the inspection voltage based on two reference voltages respectively representing a high critical threshold value and a low critical threshold value of the die under a normal operation. The inspection result indicates an operating status of the die. Thus, inspection costs are reduced and inspection efficiency is enhanced.

Proposed are a probe head for testing, through a probe, a pattern formed on a wafer, and a probe card having the same. More particularly, proposed are a probe head in which formation of a guide hole into which a probe is inserted and insertion of the probe therein are facilitated, and a probe card having the same.

A test socket comprising a guide plate with a lower surface engaged with an upper surface of a main test structure, the guide plate further including an upper surface which is parallel to the lower surface and an opening extending through the guide plate, the main test structure includes a body with one or more apertures through the upper surface and one or more probes mounted within the main test structure, the probes including a front end which extends through the apertures for engagement by a lead or terminal pad of a device to be tested, and a tail end which is secured within the main test structure by an elastomeric material.

A chip-on-film test board on which a chip-on-film is mounted according to an embodiment of the present disclosure includes a main board in which a test circuit configured to output a test pattern signal is formed, and a chip-on-film fixing part that fixes a position of the chip-on-film.

A semiconductor substrate has an internal circuit, a plurality of first pads electrically connected to the internal circuit, and one or a plurality of second pads that have a surface hardness lower than that of the plurality of first pads and are not electrically connected to the internal circuit.

A burn-in board for testing the operational integrity of memory devices includes local heating elements for each memory device under test. Each socket on the burn-in board may include a pair of opposed latch heads which move between open positions allowing a memory device to be mounted in the socket, and closed positions where the latch heads rest against the memory device to secure the device in the socket. Local heating elements may be integrated into the latch heads to ensure even heating of each memory device in the burn-in board.