A method of analyzing defects in a semiconductor device includes: collecting current data by applying a test voltage to the semiconductor device; extracting data within a decrease range from the current data; dividing the current data into a first component value and a second component value using the current data and the data extracted from within the decrease range; calculating a first quality index from the first component value satisfying a first function; and calculating a second quality index from the second component value satisfying a second function that is different from the first function.

A method of testing an integrated circuit of a device is described. Air is allowed through a fluid line to modify a size of a volume defined between the first and second components of an actuator to move a contactor support structure relative to the apparatus and urge terminals on the contactor support structure against contacts on the device. Air is automatically released from the fluid line through a pressure relief valve when a pressure of the air in the fluid line reaches a predetermined value. The holder is moved relative to the apparatus frame to disengage the terminals from the contacts while maintaining the first and second components of the actuator in a substantially stationary relationship with one another. A connecting arrangement is provided including first and second connecting pieces with complementary interengaging formations that restricts movement of the contactor substrate relative to the distribution board substrate in a tangential direction.

A socket includes: a contact probe; and an insulating support body supporting the contact probe. The contact probe includes: a first plunger to be connected with an object to be inspected; a second plunger to be connected with an inspecting board; and a spring configured to urge the first plunger and the second plunger in a direction apart from each other. In a state where a tip end of the first plunger is released, a projecting amount of the second plunger from the insulating support body is zero with a natural length of the spring.

A flexible probe card according to the present invention includes a compression layer; a transport layer coupled to the compression layer; and a contact layer coupled to the transport layer. The compression layer is formed of encapsulated closed cell polyurethane foam. The transport layer includes connectors for coupling the flexible probe card to a tester. The contact interface layer includes embedded conductive wires placed in a fixed grid pattern in a silicon rubber layer without a specific connector pattern associated either with the transport layer or a device under test.

OBJECT

To improve the strength of a probe guide and improve the abrasion resistance of the probe guide.

MEANS FOR SETTLEMENT

A guide plate 20 is formed of a silicon plate 22 having guide holes 23 respectively adapted to support contact probes 13, the inner walls of the guide holes 23 include a guide film 25 formed on the inner wall surfaces of corresponding penetration-processed holes 24 of the silicon plate 22, the cross-sectional areas of the penetration-processed holes 24 gradually increase toward a first surface of the silicon plate 22, and the film thickness of the guide film 25 gradually increases toward the first surface of the silicon plate 22. By employing such a configuration, as compared with the tilts of the inner wall surfaces of the penetration-processed holes 24, the tilts of the inner wall surfaces of the guide holes 23 can be suppressed, and the strength of the silicon plate 20 can be improved. Accordingly, the abrasion resistance of a probe guide 100 can be improved.

A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

An inspection method includes a step S20 of electrically connecting electrical signal terminals of a semiconductor device to electric connectors, and optically connecting optical signal terminals of the semiconductor device to optical connectors, a step S30 of measuring a test light output signal output from a monitoring element provided in an inspection object in response to a test input signal having been input to the monitoring element while adjusting conditions of a position and an inclination of the inspection object, and extracting conditions in which an optical intensity of the test light output signal is a predetermined determination value or greater as inspection conditions, and a step S40 of inspecting the semiconductor device under the inspection conditions.

Provided is a contact pin comprising: a hollow first plunger that includes a first contact portion provided on one end side in a first direction and a first enlarged portion which is enlarged in a second direction intersecting the first direction; a second plunger, the one end of which is inserted into the first plunger and that includes a second contact portion provided on the other end side in the first direction and a second enlarged portion provided in a protruding portion protruding from the first plunger so as to be enlarged in the second direction; and a spring provided between the first and second plungers so as to surround the first and second plungers, wherein the first enlarged portion forms a curve shape to bulge outward.

An analysis device analyzes inspection results of an inspection object which includes inspection target devices having respective electrodes on which needle marks are formed. The analysis device includes a display part for displaying an image, and an image generation part for generating an image to be displayed on the display part. The image generation part generates an analysis image based on information on inspection results with respect to the needle marks. The analysis image includes a needle mark scatter plot image showing positions of the needle marks with respect to the electrodes in each inspection target device in an overlapped manner, an inspection object map image showing a surface of the inspection object and showing needle mark inspection results with respect to the inspection target devices, and a captured image of the electrodes. Display contents of the images are linked with each other.

An inspection jig may include a frame, an electrode body provided with electrodes, conductive contactors having a wire shape, a support block having a facing surface opposite to which an inspection circuit board is disposed, guiding one ends of the contactors to the inspection points of the circuit board mounted on the facing surface, guiding other ends to the electrodes, and configured to move relatively to the frame in a moving direction which crosses the facing surface, biasing parts configured to bias the support block in a direction moving away from the electrode body and close to the circuit board, and a regulating plate disposed between the support block and the frame so as to extend in a direction from the support block to the frame, having elasticity, and having regulation of deformation in a first direction which is parallel to the facing surface and which crosses the extending direction.