G01R31/2893

TRAY ELEVATING AND LOWERING APPARATUS OF TEST HANDLER
20230024139 · 2023-01-26 · ·

A tray elevator of a test handler includes a tray mounter on which a test tray is seated and having a support part and a through hole vertically penetrating the support part, a shaft vertically extending through the through hole of the tray mounter and configured to provide a path for elevating or lowering the tray mounter, a guide bushing including an outer surface and a groove at the outer surface, inserted into the through hole of the tray mounter, and configured to move along the shaft, and a ring inserted into the groove of the guide bushing.

METHODS AND DEVICES FOR TESTING A DEVICE UNDER TEST USING TEST SITE SPECIFIC THERMAL CONTROL SIGNALING
20230228805 · 2023-07-20 ·

Embodiments of the present invention provide an automated test equipment (a “tester”) for testing a device under test, including a bidirectional dedicated real-time handler interface. Some embodiments include an interface having a trigger function, a fixed endpoint interface, an interface arranged on a test head, and/or a number of lines/communication channels adapted to a specific communication task, without separate signal lines, for example. The bidirectional dedicated real-time handler interface can be used to transmit thermal control signals, and the transmitted signals can be test site specific. The real-time signaling advantageously improves testing accuracy and efficiency.

PRESSURIZING DEVICE FOR SEMICONDUCTOR TESTING AND SEMICONDUCTOR TEST DEVICE INCLUDING THE SAME

A pressurizing device for semiconductor testing includes a tension block, a first pusher block extending through the tension block, a base plate on the first pusher block, a second pusher block on the tension block and extending through the base plate, a first spring connected to each of the first pusher block and the second pusher block, a second spring connected to each of the tension block and the base plate, a press plate on the base plate, and a press shaft coupled to the press plate. The press shaft includes a shaft hole.

Non-contact test solution for Antenna-On-Package (AOP) devices using near-field coupled RF loopback paths

A radio frequency (RF) loopback substrate or printed circuit board (PCB) which contains receive and transmit antennas located on the bottom of the loopback substrate which are aligned with the complementary transmit and receive antennas on an antenna on package (AOP) device under test. The loopback substrate receive and transmit antennas are coupled to each other. The device under test contacts are driven by a conventional tester, which causes RF circuitry in the integrated circuit to drive an AOP transmit antenna. The corresponding loopback substrate receive antenna receives the RF signal from the AOP transmit antenna and provides it to the loopback substrate transmit antennas. The integrated circuit package AOP receive antennas then receive the RF signals from the loopback substrate transmit antennas. The signals at the integrated circuit package AOP receive antennas are monitored through the integrated circuit contacts to monitor the received RF signals.

Test carrier
11693026 · 2023-07-04 · ·

A test carrier that accommodates a device under test (DUT) and has a through-hole facing the DUT, including: a movable valve that: opens by suction through the through hole such that the DUT is sucked through the through hole.

DEVICE FOR CARRYING CHIP, AND DEVICE AND METHOD FOR TESTING CHIP
20230003792 · 2023-01-05 ·

The present disclosure relates to a device for carrying a chip, and a device and a method for testing a chip. The device for carrying a chip is configured to fasten chips of different sizes, and includes a support box and a plurality of first elastic snap rings. The support box is configured to carry a chip. A first connection terminal of the first elastic snap ring is provided on a first inner side wall of the support box, a second connection terminal of the first elastic snap ring is suspended, and is configured to be in contact with the chip and provide a pressure in a first direction for the chip because an elastic body of the first elastic snap ring is in an elastically compressed state.

ASSEMBLY FOR CARRYING CHIP, ANDDEVICE AND METHOD FOR TESTING CHIP
20230003763 · 2023-01-05 ·

The present disclosure discloses an assembly for carrying a chip, and a device and a method for testing a chip. The assembly for carrying a chip is configured to fasten chips of different sizes, and includes a rotatable vertical rod, a cross beam, a first sidewall, and a second sidewall. The rotatable vertical rod is provided with a gear that surrounds the rotatable vertical rod with gear teeth. The cross beam is internally provided with a first through hole and a first chute. A top of the first sidewall is connected to a first connecting rod located in the first chute. A top of the second sidewall is connected to a second connecting rod located in the first chute. A side surface of the first connecting rod is provided with a plurality of first tooth grooves arranged linearly.

MONITOR WAFER MEASURING METHOD AND MEASURING APPARATUS
20220406636 · 2022-12-22 ·

The present invention relates to a monitor wafer measuring method and measuring apparatus. The monitor wafer measuring method comprises the following steps: fixing a product wafer, the product wafer having several alignment marks and product measuring sites corresponding respectively to the alignment marks; determining the product measuring sites according to the alignment marks; and placing a monitor wafer, a projection of the monitor wafer in a vertical direction being aligned with and coinciding with the product wafer. The present application can reduce or even eliminate positional errors of the monitor wafer during a measurement process, such that product-level measuring position accuracy can be achieved for the monitor wafer and further, the measuring machine itself and process changes can be monitored in a better way.

TEST KIT FOR TESTING A DEVICE UNDER TEST

A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having at least an interposer substrate sandwiched by a top socket and a nest.

On-wafer tuner system and method
11506708 · 2022-11-22 ·

A balanced on-wafer load pull tuner system includes an intelligent, independent and universal mechanical balancing and contact controlling device, supporting automatic microwave single or multi-probe slide screw tuners. It allows contacting and stable on-wafer testing of sub-micrometric devices. Ultra-low loss rigid airlines (bend-lines) used to connect the tuner with the semiconductor chips, in order to improve the tuning range at the DUT reference plane, transfer mechanical movements of the wafer probes attached to the rigid bend-lines, when the tuner mobile carriages move horizontally. A precisely controlled counter-weight allows contacting the DUT and balanced load pull operation by controlling the center of gravity of the assembly.