An testing method includes following operations: generating, by a signal generator, a multi-tone signal; transmitting, by the signal generator, the multi-tone signal to an input terminal of an under-test device; measuring, by a spectrum analyzer, the input terminal of the under-test device and an output terminal of the under-test device to acquire a plurality of input ripple intensities corresponding to a plurality of frequencies and acquire a plurality of output ripple intensities corresponding to the frequencies; and generating, by a control device, a plurality of power supply rejection ratios corresponding to the frequencies according to the input ripple intensities and the output ripple intensities.

A tester apparatus is described. Various components contribute to the functionality of the tester apparatus, including an insertion and removal apparatus, thermal posts, independent gimbaling, the inclusion of a photo detector, a combination of thermal control methods, a detect circuitry in a socket lid, through posts with stand-offs, and a voltage retargeting.

A test apparatus includes a test chamber in which a plurality of the semiconductor packages having a plurality of component dies is secured, an operation tester configured to conduct an operation test to the plurality of semiconductor packages to detect whether at least one semiconductor package is an operation fault package having a fault and identify a fault package point at which the operation fault package is located, a fault heat detector configured to detect a fault heat generated from the fault, and a test controller configured to control the operation tester to conduct the operation test to the plurality of semiconductor packages and control the fault heat detector subsequent to the operation test to detect the fault heat generated from the fault of the operation fault package to determine a vertical point of the fault and to determine a fault die having the fault.

A control part of a semiconductor fault analysis device outputs an alignment command that moves a chuck to a position at which a target is detectable by a first optical detection part and then aligns an optical axis of a second optical system with an optical axis of a first optical system with the target as a reference, and outputs an analysis command that applies a stimulus signal to a semiconductor device and receives light from the semiconductor device emitted according to a stimulus signal with at least one of a first optical detection part and a second optical detection part in a state in which a positional relationship between the optical axis of the first optical system and the optical axis of the second optical system is maintained.

Systems and methods for improving substrate fabrication are provided. Subsets of dies of substrates may be inspected at various points in the fabrication process to generate spectra data. The spectra data can be used to generate data that are input to a machine learning model to predict yields for the substrates.

Provided is a test method of a semiconductor device under test, the test method comprising: controlling the semiconductor device under test to an on state by inputting a control signal to the semiconductor device under test; and observing the semiconductor device under test at a time of controlling the semiconductor device under test in the on state to an off state and evaluating the semiconductor device under test, wherein the semiconductor device under test includes one semiconductor device under test or a plurality of semiconductor devices under test, and in the controlling to the on state, a length of an on-time for which the one semiconductor device under test or the plurality of semiconductor devices under test are set to the on state is adjusted based on a magnitude of a variation in a delay time of the control signal.

An objective of the present invention is to provide a system which can infer the cause of a recipe error and present a correction candidate for the recipe error. A recipe information presentation system or recipe error inference system according to the present invention: causes a learner to learn a correspondence between a recipe and an error originating from the recipe; and acquires from the learner an inference result as to whether the error occurs when a new recipe is used (refer to FIG. 1).

A system and method for evaluating the reliability of semiconductor die packages are configured to sort a plurality of semiconductor dies with a Known Good Die (KGD) subsystem based on a comparison of an inline part average testing (I-PAT) score of each of the plurality of semiconductor dies to a plurality of I-PAT score thresholds, where the semiconductor die data includes the I-PAT score for each of the plurality of semiconductor dies, where the I-PAT score represents a weighted defectivity of the corresponding semiconductor die. The semiconductor dies may be filtered to remove at-risk semiconductor dies prior to sorting. The semiconductor die data may be received from a plurality of semiconductor die supplier subsystems. The KGD subsystem may transmit semiconductor die reliability data about the sorted plurality of semiconductor dies to a plurality of semiconductor die packager subsystems.

A timer circuit includes a plurality of n-type field effect transistors (NFETs) powered by a current source, a plurality of electromigration detection elements each electrically connected to a respective NFET of the plurality of NFETs, and a read-out circuit electrically connected to the plurality of electromigration detection elements to meter usage of each of the NFETs.

A tester apparatus is described. Various components contribute to the functionality of the tester apparatus, including an insertion and removal apparatus, thermal posts, independent gimbaling, the inclusion of a photo detector, a combination of thermal control methods, a detect circuitry in a socket lid, through posts with stand-offs, and a voltage retargeting.