A wafer chip testing method and apparatus, an electronic device and a storage medium are provided. The testing method includes: comparing each configuration parameter of each wafer chip with a standard specification threshold interval of a corresponding parameter type, and marking as marked test parameters configuration parameters which do not belong to the standard specification threshold intervals; and inputting all marked test parameters of individual wafer chip into a combination rule judgment function respectively, outputting wafer chip(s) which does not conform to any one or more rules in the combination rule judgment function, and determining the wafer chip(s) as unqualified wafer chip(s).

An integrated circuit method processes parametric data for each integrated circuit die in a plurality of integrated circuit die to determine an expected data pattern, screens integrated circuit die by comparing a data pattern corresponding to a plurality of parametric data for the integrated circuit die to an expected data pattern and, responsive to the comparing, determining whether a difference between the data pattern corresponding to a plurality of parametric data for the predetermined integrated circuit die and the expected data pattern is beyond a tolerance.

A fault analysis method comprises: receiving fault data from wafer level testing that identifies locations and test results of a plurality of die; applying a kernel transform to the fault data to produce cluster data, where the kernel transform defines a fault impact distribution that defines fault contribution from the failed die to local die within an outer radial boundary of the fault impact distribution. Applying the kernel transform comprises: centering the fault impact distribution at a location of each die that failed wafer level testing, associating each local die that falls within the outer radial boundary with a respective fault contribution value according to the fault impact distribution, and accruing fault contribution values associated with each respective die of the plurality of die to produce a cluster value for the respective die, which correlates to a probability of failure of the respective die at a future time.

Methods for selecting integrated circuit dies based on pre-determined criteria are disclosed. A disclosed method includes binning tools that characterizes multiple integrated circuit dies based on performance attributes. Each integrated circuit die is labeled with an identifier that represents bin location of the integrated circuit die within a die storage structure. A user can search for integrated circuit dies that matches certain performance grading by providing a performance description to an input interface on testing equipment. A tester is then configured to perform a screening to identify the physical locations of integrated circuit dies that match the retrieved identifiers from the die storage structure.

A device and a method for monitoring and analysis utilize unintended electromagnetic emissions of electrically powered components, devices or systems. The emissions are received at the antenna and a receiver. A processor processes and measures change or changes in a signature of the unintended electromagnetic emissions. The measurement are analyzed to both record a baseline score for future measurements and to be used in determining status and/or health of the analyzed system or component.

Systems, apparatuses, and methods for enabling sensor discovery in autonomous devices herein. An example device to perform system-level verification predictions includes a neural network circuit including a neural network. During a first phase, the neural network circuit to train the neural network using respective assembly-level test data and the system-level verification test data associated with each of a first plurality of semiconductor dice. The first plurality of semiconductor dice is produced from a plurality of training wafers. During a second phase, the neural network circuit to determine, using the neural network, a system-level pass/fail decision for each of second plurality of semiconductor dice based on respective assembly-level test data associated with each of the second plurality of semiconductor dice. The second plurality of semiconductor dice is produced from a plurality of production wafers.

Embodiments described herein provide a method for identifying failure patterns in electronic devices. The method begins when a limit is determined for a parameter of interest. A series of the electronic devices is then tested using the limit of the parameter of interest. Failing devices are then identified and x and y coordinate values are plotted. Pattern recognition may be used to determine if the failures shown on the coordinate plot fit a failure pattern. The limit of the parameter of interest is then regressed in steps to the mean value of the failing devices and the electronic devices are retested. The failure pattern of the retested devices is examined to determine if the failure pattern fits a failure pattern. If the failure pattern fits a failure pattern then the parameter of interest may be found to affect the yield rate of production for the electronic devices.

The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

Systems and methods are provided for testing remote frequency identification (RFID) straps. A testing system includes an amplifier electrically coupled to an inductor or inductive component. The system further includes a pair of contact points to be placed in contact with a pair of contact pads of an RFID strap. Connecting the contact points and the contact pads places the RFID strap in parallel with the inductor to define a resonant circuit. The characteristics of the resonant circuit as an oscillator depend at least in part on the capacitance and the resistance of the RFID strap. As such, the characteristics of the resonant circuit as an oscillator may be monitored to determine the capacitance and/or the resistance of the RFID strap. One or more characteristics of the RFID strap may be compared to one or more threshold values to determine whether the RFID strap is acceptable or defective.

Systems and methods for sorting an electronic device undergoing a final test operation in accordance with a test program, into one of a plurality of bins. In one embodiment, an evaluator defines the binning of the electronic device while the device is still socketed, and the defined binning may or may not concur with the binning assigned by the test program.