A test information management device manages test information relating to a test carried out by receiving a test signal output from a first device in a second device. The test information management device includes a linker configured to link together first information including information representing an output state of the test signal in the first device and second information including image information representing reception results of the test signal in the second device using at least one of identification information for identifying the first device or the second device and times at which the first information and the second information are generated.

A method of testing semiconductor devices includes contacting bond pads coupled to integrated circuitry on a first die of a plurality of interconnected die on a substrate using a probe system having probes and probe tests including parametric tests, continuity tests, and a kill die subroutine. Probe tests using the probe program are performed. Die are binned into a first bin (Bin 1 die) for being a good die for all probe tests, or a second bin (Bin 2 die) for failing at least one of continuity tests and parametric tests. The Bin 2 die are divided into a first sub-group that failed the continuity tests and a second sub-group that do not fail the continuity tests. A kill die subroutine is triggered including applying power sufficient to selectively cause damage to the second sub-group of Bin 2 die to generate a continuity failure and thus generate kill die.

A value representative of a dispersion of a propagation delay of assemblies of electronic components is determined. A component test structure includes stages of components and a logic circuit connected in a ring. Each stage includes two assemblies of similar components configured to conduct a signal. A test device is configured to obtain values of the component test structure and to perform operations on these values.

In a method of analyzing a semiconductor device, output values of semiconductor devices are measured, population data including the output values in connection with values of design attributes of the semiconductor devices is determined, outlier output values are extracted from among the output values included in the population data to determine discriminated data, and a weak value of a weak design attribute, which causes the outlier output values, is determined based on a difference between a ratio of a number of outlier output values, which are related with respective values of the design attributes, to a total number of the outlier output values included in the discriminated data, and a ratio of a number of output values, which are related with respective values of the design attributes, to a total number of the output values included in the population data.

Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

A tester apparatus is described. Various components contribute to the functionality of the tester apparatus, including an insertion and removal apparatus, thermal posts, independent gimbaling, the inclusion of a photo detector, a combination of thermal control methods, a detect circuitry in a socket lid, through posts with stand-offs, and a voltage retargeting.

Automatically identifying defect-based test coverage gaps in semiconductor devices includes determining a plurality of apparent killer defects on one or more semiconductor devices with a plurality of semiconductor dies based on characterization measurements of the one or more semiconductor devices acquired by one or more semiconductor fabrication subsystems, determining at least one semiconductor die which passes at least one test based on test measurements acquired by one or more test tool subsystems, correlate the characterization measurements with the test measurements to determine at least one apparent killer defect on the at least one semiconductor die which passes the at least one test, and determining one or more gap areas on the one or more semiconductor devices for defect-based test coverage based on the at least one apparent killer defect on the at least one semiconductor die which passes the at least one test.

A method of sorting an electronic device includes receiving first data generated by a test tool that is performing a test operation on the electronic device according to a test program, and a provisional binning assignment for the electronic device determined from the first data. The method also includes defining a permanent binning assignment for the electronic device based at least in part on applying a first algorithm and a second algorithm to the first data, the first algorithm and the second algorithm being different. The method further includes outputting the permanent binning assignment so that after the test operation is completed, the electronic device is removed from the test tool and placed in one of a plurality of bins according to the permanent binning assignment.

The invention discloses a test method for high-speed signal frequency measurement and signal integrity. Through the combination of integrated circuit digital-analog test system and programmable digital system, the trigger signal of the test system is synchronized with the digital signal of the peripheral test circuit to generate 100 M square wave and data to verify whether the chip can work normally. When the enabling signals of the integrated circuit digital-analog test system are detected by the peripheral test circuit, the corresponding square wave signal of 100 M or the preset data signal are given to the tested digital chip. The two enabling signals have the same priority, and then sample the output of the tested digital chip, wherein, the collected output waveform needs to be logically calculated and divided into a 10 M square wave, and the frequency measurement is carried out, then the processed results are returned to the test system. The test system accurately selects the chip with correct function according to the data, and eliminates the chip with abnormal work.

A chip module includes a chip having a front side and a rear side, a chip carrier having an upper side facing the chip, a contact layer formed of an electrically conductive material and arranged on the upper side of the chip carrier between the rear side of the chip and the upper side of the chip carrier, and an electrically conductive adhesive arranged on an upper side of the contact layer facing the chip. The electrically conductive adhesive connects the upper side of the contact layer and the rear side of the chip. The contact layer has a plurality of regions electrically insulated from each other and each electrically connected to the chip by the electrically conductive adhesive.