A method of copper hillock detecting includes the following steps. A testkey structure is disposed on a substrate, wherein the testkey structure includes a lower metallization layer, an upper metallization layer, and a dielectric layer between the lower metallization layer and the upper metallization layer. A force voltage difference is applied to the lower metallization layer and the upper metallization layer under a test temperature and stress time. A changed sensing voltage difference to the lower metallization layer and the upper metallization layer is detected for detecting copper hillock.

Embodiments of the present invention may include a method and a system for detection of counterfeit and cyber electronic components by obtaining one or more features from a plurality of electronic components of a first type and from a plurality of N electronic components of a second type, processing the one or more features to create a unique model related to an electronic component of the first type and to an electronic component of the second type, examining a detected electronic component by obtaining one or more features of the detected electronic component, executing the unique model with the one or more features of the detected electronic component and determining if the detected electronic component is an authentic electronic component of the first type or the second type.

Aspects of the disclosure provide an APC system. The APC system can include a first processing tool that performs a first process on a target wafer, a second processing tool that performs a second process on the target wafer, and a prediction server that includes a prediction model for predicting a characteristic of the target wafer resulting from the first process using real-time data from the first process performed on the target wafer. Parameters of the prediction model can be updated by historical data of previous first processes. The APC system can also include a controller that is coupled to the first and second processing tools. After the first processing tool performs the first process on the target wafer, the controller can instruct the second processing tool to perform an adjusted second process on the target wafer based on the characteristic of the target wafer predicted by the prediction model.

A chip crack detection apparatus includes a function circuit and a die crack detection module surrounding the function circuit. The die crack detection module includes a front-end-of-line device layer, a laminated structure on the front-end-of-line device layer that includes a conducting wire in the laminated structure, a detection interface, and a capacitor at the front-end-of-line device layer. A first end of the conducting wire is configured to connect to a positive electrode of a power supply. A second end of the conducting wire is configured to connect to a negative electrode of the power supply. The capacitor is connected in parallel between the first end and the second end of the conducting wire. The detection interface is coupled with the conducting wire between the first end and the second end of the conducting wire. The detection interface is configured to detect whether a die crack occurs in the chip.

A testing circuit includes a first circuit and a second circuit. The first circuit and second circuit have a first capacitor and a second capacitor. The first circuit is connected to a first transistor. The second circuit is connected to a second transistor. A first inductor has a first terminal connected to an input of the testing circuit and a second terminal connected to a source of the second transistor. A first diode has an anode connected to ground and a cathode connected to the second terminal of the first inductor. The second capacitor has a first terminal connected to a drain of the second transistor and a second terminal connected to ground. The first capacitor has a first terminal connected to the input of the testing circuit and a second terminal connected to ground.

A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.

Disclosed are a method, device and system for health monitoring of SoC. The method includes: acquiring in real time sensor data of sensors monitoring SoC performance, the sensor data including reliability degradation sensor data, temperature sensor data, noise sensor data and current sensor data; extracting characteristic data representative of the SoC performance from the sensor data; performing analysis and prediction on the characteristic data in real time by using a prediction algorithm to obtain a performance state and a performance degradation trend of the SoC; outputting performance state information and performance degradation trend information of the SoC. The disclosed method, device and system for health monitoring of SoC can monitor the performance state of the SoC in real time and predict the performance degradation trend of the SoC in real time.

An electronic device including a processor and a sensor may be provided. The processor obtains a first degree of degradation of a first core based on a first parameter value associated with a lifetime of the first core and a first operating level associated with an operation of the first core. The processor obtains a second degree of degradation of a second core based on a second parameter value associated with a lifetime of the second core and a second operating level associated with an operation of the second core. The processor schedules a task of the first core and the second core based on the first degree of degradation and the second degree of degradation. The sensor provides the first parameter value and the first operating level to the first core and the second parameter value and the second operating level to the second core.

A system, method, and computer-readable medium are disclosed for automated component serialization. A group of components that are of the same component to be used in a computer system are identified. One of the components is separated and labeled with serialization information. The labeled serialized information is verified and entered into an enterprise resource planning system. The process continues until all the group of components are labeled and verified.

A computer-implemented method to detect a damaged tunneling magnetoresistance (TMR) sensor includes applying current at at least two different current values to the TMR sensor and measuring a resistance, R.sub.TMR, at each current value. The method also includes measuring a slope in resistance vs. bias current, RD.sub.SLP, using the measured resistances R.sub.TMR and the at least two different current values. The method includes calculating a ΔRD.sub.SLP value as a difference between the RD.sub.SLP value and an expected value, RD.sub.SLP-expected, for the TMR sensor. The method includes determining whether the ΔRD.sub.SLP value is within a predefined range. In response to determining that the ΔRD.sub.SLP value is outside the predefined range, the method includes outputting an indication that the TMR sensor fails. In response to determining that the ΔRD.sub.SLP value is within the predefined range, the method includes outputting an indication that the TMR sensor passes.