A test method for a semiconductor device includes: loading a test tray having semiconductor devices of first and second lots arranged thereon into a test chamber; storing lot information of each of the semiconductor devices; performing a test program on each of the semiconductor devices; obtaining ID information of each of the semiconductor devices; matching the ID information with the lot information to generate lot sorting information; and sorting the semiconductor devices based on results of the test program and the lot sorting information.

In order to analyze information obtained from a measurement system and to manage the measurement system, there is provided an analysis apparatus including: an acquisition unit configured to acquire a plurality of measured values obtained by a test apparatus measuring a device under measurement; an analysis unit configured to analyze the plurality of measured values to extract dispersion of a measured value; and a management unit configured to detect an error in the test apparatus based on the dispersion of the measured value. Further, in order to solve the above problem, there is provided an analysis method. Further, in order to solve the above problem, there is provided a recording medium having recorded thereon an analysis program.

A multi-station concurrent testing method, comprising: a step A in which the control station controls the handler to send SOT signal(s) of corresponding testing station(s) based on previous testing results at adjacent testing stations of the testing stations; a step B in which the control station constructs an SOT signal sequence based on the received SOT signal(s) and in correspondence to orders of the testing stations; and a step C in which the control station compares the SOT signal sequence and an SOT signal prediction value sequence generated by the control station, wherein if the SOT signal sequence and the SOT signal prediction value sequence match, the corresponding testing station(s) executes the test of device(s) under test, and otherwise, the handler is controlled to purge the devices under test at the testing stations, the SOT signal prediction value sequence is generated based on previous testing results at the testing stations.

A method for predicting yield for a semiconductor process. A particular type of wafer is fabricated to have a first set of features disposed on the wafer, with a wafer map identifying a location for each of the first set of features on the wafer. Data from wafer acceptance tests and circuit probe tests is collected over time for wafers of that particular type as made in a semiconductor fabrication process, and at least one training dataset and a least one validation dataset are created from the collected data. A second set of “engineered” features are created and also incorporated onto the wafer and wafer map. Important features from the first and second sets of features are identified and selected, and using those important features as inputs, a number of different process models are run, with yield as the target. The results of the different models can be combined, for example, statistically.

A model is generated for predicting failures at the wafer production level. Input data from sensors is stored as an initial dataset, then data exhibiting excursions or useless impact is removed from the dataset. The dataset is converted into target features, where the target features are useful in predicting whether a wafer will be normal or not. A trade-off between positive and negative results is selected, and a plurality of predictive models are created. The final model is selected based on the trade-off criteria, and deployed.

A test apparatus includes a test chamber in which a plurality of the semiconductor packages having a plurality of component dies is secured, an operation tester configured to conduct an operation test to the plurality of semiconductor packages to detect whether at least one semiconductor package is an operation fault package having a fault and identify a fault package point at which the operation fault package is located, a fault heat detector configured to detect a fault heat generated from the fault, and a test controller configured to control the operation tester to conduct the operation test to the plurality of semiconductor packages and control the fault heat detector subsequent to the operation test to detect the fault heat generated from the fault of the operation fault package to determine a vertical point of the fault and to determine a fault die having the fault.

An inspection system is provided that includes a microscope that scans a sample with a beam that is an incident electron beam, and an image processing device that controls the microscope. The image processing device performs: an acquisition process of acquiring a plurality of images relating to brightness based on an amount of a signal electron detected from the sample a result of controlling the microscope according to a s and irradiating the sample with the beam, the plurality of image acquisition condition being multiple combinations of different irradiation amounts of the beam per unit length; a first generation process of generating a plurality of actually measured profiles that show a relationship between an irradiation position of the beam in the sample and the brightness of the sample, based on the plurality of images acquired in the acquisition process; and an output process of outputting an electrical contact characteristic of the sample based on the plurality of actually measured profiles generated in the first generation process.

Wafer test control and methodologies are provided for resuming the probing of a wafer, in connection with random, distributed or statistical wafer probing. The resumption of testing may occur after an interruption of a previous probe of the wafer and removal of the wafer from a testing chuck. Parameter settings are retained in addition to probe results from the previous wafer probe session in order to construct a resume probe map according to applicable probing rules and conditions. Wafer probing may be restarted according to the resume probe map.

A wafer surface test preprocessing device includes a chamber; a supporting component disposed in the chamber; an atomizer connected to a lateral side of the chamber; a cooling component connected to a bottom of the chamber; and a lid disposed on a top of the chamber. With the wafer surface test preprocessing device having the cooling component to thereby dispense with a ventilation device and collect hydrofluoric acid residues in the chamber at the bottom of the chamber, thereby saving costs and time effectively.

Disclosed herein are testing apparatus and methods to identify latent defects in IC devices based on capacitive coupling between bond wires. Bond wires may have latent defects that do not appear as hard shorts or hard opens at the time of testing, but may pose a high risk of developing into hard shorts or hard opens over time. A latent defect may form when two adjacent bond wires are disturbed to become close to each other. According to some embodiments, capacitive coupling between a pair of pins may be used to provide an indication of a near-short latent defect between bond wires connected to the pair of pins.