The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

Described are various embodiments of an ion beam delayering system and method, topographically enhanced sample produced thereby, and imaging methods and systems related thereto. In one embodiment, a method comprises: identifying at least two materials in an exposed surface of the sample and predetermined operational characteristics of an ion beam mill that correspond with a substantially different ion beam mill removal rate for at least one of the materials; operating the ion beam mill in accordance with the predetermined operational characteristics to simultaneously remove the materials and introduce or enhance a topography associated with the materials and surface features defined thereby; acquiring surface data; and repeating the operating and acquiring steps for at least one more layer.

The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

Multiple planes within the sample are exposed from a single perspective for contact by an electrical probe. The sample can be milled at a non-orthogonal angle to expose different layers as sloped surfaces. The sloped edges of multiple, parallel conductor planes provide access to the multiple levels from above. The planes can be accessed, for example, for contacting with an electrical probe for applying or sensing a voltage. The level of an exposed layer to be contacted can be identified, for example, by counting down the exposed layers from the sample surface, since the non-orthogonal mill makes all layers visible from above. Alternatively, the sample can be milled orthogonally to the surface, and then tilted and/or rotated to provide access to multiple levels of the device. The milling is preferably performed away from the region of interest, to provide electrical access to the region while minimizing damage to the region.

The present disclosure discloses a method for wafer-level chip scale packaged wafer testing. The method comprises: dicing a wafer-level chip scale packaged wafer into a plurality of wafer strips each comprising a plurality of un-diced chip scale packaged devices; fixing the wafer strips onto a plurality of corresponding strip carriers respectively; testing the chip scale packaged devices of the wafer strips fixed onto the strip carriers by a testing equipment; and dicing the tested wafer strips into a plurality of individual chip scale packaged devices. Since the proposed method does not involve loading a multitude of diced chips into sockets one by one, but that a limited number of wafer strips are loaded onto corresponding strip carriers, flow jam is avoided.

The present disclosure discloses a method for wafer-level chip scale packaged wafer testing. The method comprises: dicing a wafer-level chip scale packaged wafer into a plurality of wafer strips each comprising a plurality of un-diced chip scale packaged devices; fixing the wafer strips onto a plurality of corresponding strip carriers respectively; testing the chip scale packaged devices of the wafer strips fixed onto the strip carriers by a testing equipment; and dicing the tested wafer strips into a plurality of individual chip scale packaged devices. Since the proposed method does not involve loading a multitude of diced chips into sockets one by one, but that a limited number of wafer strips are loaded onto corresponding strip carriers, flow jam is avoided.

Disclosed is in particular a device (2) for stressing an integrated circuit (1) including an electronic chip (10) mounted in a housing (12), the device including a source (20) of thermal stress. The device (2) also includes a thermally conductive coupling member (22), designed to be thermally coupled to the source (20) of thermal stress during the stressing operation. The coupling member (22) includes an end (220) whose geometry is suitable for being introduced into an aperture with a predefined geometry, to be made in the housing (12) of the integrated circuit (1) so as to thermally couple a coupling face (222) of this end (220) with a face (102) of the electronic chip (10).

The various technologies presented herein relate to utilizing visible light in conjunction with a thinned structure to enable characterization of operation of one or more features included in an integrated circuit (IC). Short wavelength illumination (e.g., visible light) is applied to thinned samples (e.g., ultra-thinned samples) to achieve a spatial resolution for laser voltage probing (LVP) analysis to be performed on smaller technology node silicon-on-insulator (SOI) and bulk devices. Thinning of a semiconductor material included in the IC (e.g., backside material) can be controlled such that the thinned semiconductor material has sufficient thickness to enable operation of one or more features comprising the IC during LVP investigation.

A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

Milling using a scanning probe microscope with a diamond tip removes a layer of material and produces a surface that is sufficiently smooth that it can be probed using a nanoprober to provide site-specific sample preparation and delayering. Diamond milling provides in situ, localized, precision delayering inside of a nanoprobing tool, thereby decreasing the turnaround time for integrated circuit analysis. Furthermore, unlike focused ion beam delayering, the diamond tip should not alter the electrical characteristics of the integrated circuit.