G01R31/3025

Interface to full and reduced pin JTAG devices
11630151 · 2023-04-18 · ·

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

SYSTEM FOR TESTING ANTENNA-IN-PACKAGE MODULES AND METHOD FOR USING THE SAME

A system for testing antenna-in-package (AiP) modules and a method for using the same is disclosed. Firstly, AiP modules respectively receive RF signals from a testing transmitting antenna. Then, at least one of the power and the phase of each of the RF signals is adjusted to generate modulated RF amplified signals as recognition tags with difference. The RF amplified signals are received from each control integrated circuit (IC) and the power of the modulated RF amplified signals is summed to generate a net mixed test signal. Finally, the test signal is received and RF properties corresponding to at least one of the power and the phase of each of the RF amplified signals as recognition tags are obtained. The method can simultaneously test a plurality of AiP modules to shorten the test time.

Test circuit and method

A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.

TESTBENCHES FOR ELECTRONIC SYSTEMS WITH AUTOMATIC INSERTION OF VERIFICATION FEATURES

A system and method are disclosed for assembling a testbench for evaluating electronic systems. The method includes assembling large testbenches by using verification features associated with functional components, automatically creating component connections, and statistically checking the testbench prior to generation and simulation. The system includes a computer system that implements the method.

MODULE AND METHOD FOR INITIALIZING AND CALIBRATING A PRODUCT DURING THE MANUFACTURE THEREOF

A module for initializing and calibrating a product during the manufacture of the product in a manufacturing environment, wherein the module is able to be arranged on the product and wherein the module has a first interface for wireless data transmission between the module and the manufacturing environment, a second interface for establishing a data connection between the module and the product, an electrical energy source and a data processing unitft. The module is designed to supply the product at least temporarily with energy by way of the energy source, to establish a data connection with the product via the second interface, to perform test and/or calibration routines on the product via the second interface, wherein the data processing unit generates test and/or calibration data during the performance of the test and/or calibration routines, and to transmit the test and/or calibration data to the manufacturing environment via the first interface.

Measurement system for characterizing a device under test

In a measurement system, a signal probing circuit may provide probed signals by probing voltages and currents and/or incident and reflected waves at a port of a device under test (DUT). A multi-channel receiver structure may include receivers that receive two probed signals from the signal probing hardware circuit, each receiver having its own sample clock derived from a master clock and further having a respective digitizer for digitizing a corresponding one of the two probed signals. A synchronization block, external to the receivers and including a reference clock derived from the master clock, may enable the two probed signals to be phase coherently digitized across the receivers by synchronizing the respective sample clocks of the receivers while the reference clock is being shared with the receivers. A signal processing circuit may then process the phase coherently digitized probed signals.

Apparatus and method for wireless testing of a plurality of transmit paths and a plurality of receive paths of an electronic device

An apparatus for wireless testing, wherein the apparatus includes a test interface, a test generator, a test module, and an analysis module. The test interface is coupled to an electronic device and is configured to transmit data to the electronic device and to receive data from the electronic device. The test generator drives the electronic device through the test interface to vary the beam direction. The test module determines a plurality of transmit values of a transmit parameter based on the test signal wirelessly received from the electronic device using at least one static antenna for receiving the test signal. Each transmit value of the transmit parameter is associated with a different beam direction. The analysis module provides an assessment of the plurality of transmit paths of the electronic device based on the plurality of transmit values.

Probe card including wireless interface and test system including the same

A probe card for testing electrical properties of a device under test (DUT) includes a plurality of semiconductor devices, which includes a substrate; and at least one transmission antenna, which is implemented as a chip on film (COF) type and attached to the substrate, wirelessly transmitting at least one of electric power and data to each of the plurality of semiconductor devices.

DEVICES AND METHODS FOR TESTING OF FAR-FIELD WIRELESS CHARGING
20230168299 · 2023-06-01 ·

Disclosed is a device for testing of far-field wireless charging, including a first transceiver configured to conduct a far-field wireless power transfer between the device and a device under test, DUT; a second transceiver configured to conduct a data transfer between the device and the DUT; and a processor configured to establish a figure of merit of a wireless charging of the DUT in dependence of the power transfer and the data transfer.

TEST CIRCUIT AND METHOD

A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.