An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

A semiconductor device examination method includes a step of acquiring a first interference waveform based on signals from a plurality of drive elements according to light from a first light beam spot including the plurality of drive elements in a semiconductor device, a step of acquiring a second interference waveform based on signals from the plurality of drive elements according to light from a second light beam spot having a region configured to partially overlap the first spot and including the plurality of drive elements, and a step of separating a waveform signal for each of the drive elements in the first and second spots based on the first and second interference waveforms.

A semiconductor device examination method includes a step of acquiring a first interference waveform based on signals from a plurality of drive elements according to light from a first light beam spot including the plurality of drive elements in a semiconductor device, a step of acquiring a second interference waveform based on signals from the plurality of drive elements according to light from a second light beam spot having a region configured to partially overlap the first spot and including the plurality of drive elements, and a step of separating a waveform signal for each of the drive elements in the first and second spots based on the first and second interference waveforms.

A package substrate may include a circuit and a leaky surface wave launcher. The circuit may perform engineering tests and end-user operations using sideband signals. The leaky surface wave launcher may perform near field wireless communication. The leaky surface wave launcher may include a via and a strip line. The via may be electrically coupled to the circuit. The via may provide the sideband signals to and receive the sideband signals from the circuit. The strip line may be electrically coupled to the via. The strip line may be excited by the sideband signals to wirelessly couple the leaky surface wave launcher with an external device. The strip line and the via may be unbalanced such that the strip line generates a leaky wave that propagates at least a portion of the package substrate and an environment proximate the package substrate.

A package substrate may include a circuit and a leaky surface wave launcher. The circuit may perform engineering tests and end-user operations using sideband signals. The leaky surface wave launcher may perform near field wireless communication. The leaky surface wave launcher may include a via and a strip line. The via may be electrically coupled to the circuit. The via may provide the sideband signals to and receive the sideband signals from the circuit. The strip line may be electrically coupled to the via. The strip line may be excited by the sideband signals to wirelessly couple the leaky surface wave launcher with an external device. The strip line and the via may be unbalanced such that the strip line generates a leaky wave that propagates at least a portion of the package substrate and an environment proximate the package substrate.

According to various examples, a method for non-destructive detection of defects in a semiconductor die is described. The method may include positioning an emitter above the semiconductor die. The method may include generating an emitted wave using the emitter that is directed to a focal point on a surface of the die. The method may include generating a reflected wave from the focal point. The focal point may act as a point source reflecting the emitted wave. The method may include positioning a receiver above the die to receive the reflected wave. The method may also include measuring the reflected wave to detect modulations in amplitude in the reflected wave.

A defect inspection apparatus may include a sensor block, a measuring block, a controller and a storage. The Sensor block may include a plurality of sensors arranged in a zigzag pattern to induce an eddy current to the semiconductor die. The measuring block may be configured to apply an oscillation signal of a set frequency to the sensor block and to receive a change in the set frequency of the oscillation signal. The controller configured to determine whether or not the semiconductor die includes a defect based on the change in the set frequency of the oscillation signal. The storage configured to store the change in the set frequency of the oscillation signal caused by the eddy current in the semiconductor die and position information of the defect in the semiconductor die.

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.