According to various examples, a method for non-destructive detection of defects in a semiconductor die is described. The method may include positioning an emitter above the semiconductor die. The method may include generating an emitted wave using the emitter that is directed to a focal point on a surface of the die. The method may include generating a reflected wave from the focal point. The focal point may act as a point source reflecting the emitted wave. The method may include positioning a receiver above the die to receive the reflected wave. The method may also include measuring the reflected wave to detect modulations in amplitude in the reflected wave.

A test system for testing RF PCBs including an RF probe for interfacing an intermediate node of each RF PCB, an RF source providing an RF test signal, a reflectometer, and a test measurement system that makes a pass/fail determination of each RF PCB using a measured reflection coefficient. Each RF PCB includes an IC matching circuit and an antenna matching circuit coupled between an RFIC and an antenna, in which the intermediate RF node is between the matching circuits. The reflectometer outputs a measured reflection coefficient indicative of a comparison between a reflected RF signal and the RF test signal. The measured reflection coefficient may be corrected using error values based on a calibration procedure using a calibration kit with modified RF PCBs with known loads. The modified RF PCBs are measured with a network analyzer and the test system to calculate the error values used for production testing.

A test system for testing RF PCBs including an RF probe for interfacing an intermediate node of each RF PCB, an RF source providing an RF test signal, a reflectometer, and a test measurement system that makes a pass/fail determination of each RF PCB using a measured reflection coefficient. Each RF PCB includes an IC matching circuit and an antenna matching circuit coupled between an RFIC and an antenna, in which the intermediate RF node is between the matching circuits. The reflectometer outputs a measured reflection coefficient indicative of a comparison between a reflected RF signal and the RF test signal. The measured reflection coefficient may be corrected using error values based on a calibration procedure using a calibration kit with modified RF PCBs with known loads. The modified RF PCBs are measured with a network analyzer and the test system to calculate the error values used for production testing.

A test method for a semiconductor device includes determining a contact failure between a first semiconductor chip and a second semiconductor chip during assembly of a semiconductor package including the first semiconductor chip and the second semiconductor chip, using a test circuit embedded in the first semiconductor chip, and after the assembly of the semiconductor package, determining whether the semiconductor package is defective by using the test circuit.

An inspection device (10) includes a fixing portion (200) fixing a semiconductor device (500) being a DUT and an antenna portion (30) inspecting the semiconductor device (500). The fixing portion (200) defines a hole (210) exposing at least a portion of the semiconductor device (500). At least a portion of the inside surface of the hole (210) in the fixing portion (200) includes a step portion.

As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of an electrode pad of a TEG to facilitate the evaluation of electrical characteristics. According to the present invention, the above described problem can be solved by arranging a plurality of probes in a fan shape or manufacturing the probes with micro electro mechanical systems (MEMS) technology.

A fault isolation analysis method includes: providing a package structure in which there is an electrical fault; detecting whether the electrical fault is in interconnecting wires, and if the electrical fault is in the interconnecting wires, determining that the electrical fault is caused by the interconnecting wire; and if the electrical fault is not in the interconnecting wires, breaking the interconnecting wires to electrically isolate the chip structure from the substrate, then detecting whether the electrical fault is in the structure, and if the electrical fault is able to be detected, determining that the electrical fault is caused by the substrate, or if the electrical fault is not able to be detected, determining that the electrical fault is caused by the chip structure.

A fault isolation analysis method includes: providing a package structure in which there is an electrical fault; detecting whether the electrical fault is in interconnecting wires, and if the electrical fault is in the interconnecting wires, determining that the electrical fault is caused by the interconnecting wire; and if the electrical fault is not in the interconnecting wires, breaking the interconnecting wires to electrically isolate the chip structure from the substrate, then detecting whether the electrical fault is in the structure, and if the electrical fault is able to be detected, determining that the electrical fault is caused by the substrate, or if the electrical fault is not able to be detected, determining that the electrical fault is caused by the chip structure.

Provided is an immunity evaluation system that enables design feedback in consideration of a subject wiring and an improvement amount for improving an electromagnetic noise resistance of a circuit board. An immunity evaluation device includes: a storage unit configured to store characteristic data including probe-circuit board wiring coupling characteristics which are determined by a combination of a near-field probe and circuit board characteristics, and a test result; and an IC reaching signal level estimation unit configured to estimate a signal level reaching a terminal of an evaluation target IC. The immunity evaluation device receives board design information, information of the near-field probe, and test waveform instruction information of a signal applied to the near-field probe. The IC reaching signal level estimation unit reads the coupling characteristics from the storage unit based on the board design information of a test subject circuit board and the information of the near-field probe, and outputs a value of the IC reaching signal level reaching a terminal of the evaluation target IC from the board design information of the test subject circuit board, the information of the near-field probe, and the coupling characteristics.

A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. The scanning system is configured to updated the time-dependent map of the emissions based on a transformation of an underlying time-resolved waveform at certain intervals and corresponding to at least one location and generating a pseudo image of the DUT.