In some examples, systems and methods may be used to improve functional safety of analog or mixed-signal circuits, and, more specifically, to anomaly detection to help predict failures for mitigating catastrophic results of circuit failures. An example may include using a machine learning model trained to identify point anomalies, contextual or conditional anomalies, or collective anomalies in a set of time-series data collected from in-field detectors of the circuit. The machine learning models may be trained with data that has only normal data or has some anomalous data included in the data set. In an example, the data may include functional or design-for-feature (DFx) signal data received from an in-field detector on an analog component. A functional safety action may be triggered based on analysis of the functional or DFx signal data.

In some examples, systems and methods may be used to improve functional safety of analog or mixed-signal circuits, and, more specifically, to anomaly detection to help predict failures for mitigating catastrophic results of circuit failures. An example may include using a machine learning model trained to identify point anomalies, contextual or conditional anomalies, or collective anomalies in a set of time-series data collected from in-field detectors of the circuit. The machine learning models may be trained with data that has only normal data or has some anomalous data included in the data set. In an example, the data may include functional or design-for-feature (DFx) signal data received from an in-field detector on an analog component. A functional safety action may be triggered based on analysis of the functional or DFx signal data.

An integrated circuit and a method of self-testing the integrated circuit are provided. The method comprises: generating a reference voltage at an output of a reference circuit; initiating a test of the reference circuit during a test mode; determining whether the test of the reference circuit passes; and comparing, if the test of the reference circuit passes, a first voltage with the reference voltage. The disclosed test method provides for more complete testing of the integrated circuit.

Provided is a test circuit configured to receive an inspection command from automatic test equipment (ATE) and test a device under test (DUT), and the test circuit includes a plurality of analog inspection circuits electrically connected to the DUT to test an operation thereof, and a digital control circuit configured to control operations of the analog inspection circuits, wherein the digital control circuit and the analog inspection circuits are located apart from each other.

Provided is a test circuit configured to receive an inspection command from automatic test equipment (ATE) and test a device under test (DUT), and the test circuit includes a plurality of analog inspection circuits electrically connected to the DUT to test an operation thereof, and a digital control circuit configured to control operations of the analog inspection circuits, wherein the digital control circuit and the analog inspection circuits are located apart from each other.

An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal.

An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal.

The present invention provides a semiconductor device and a failure detection method capable of detecting an excessive variation among elements that constitute an analog circuit as a failure. According to an embodiment, a semiconductor device 1 includes: an AD converter 11; a digital assist circuit 12 that corrects an error of a digital signal Do corresponding to an analog signal Ain processed by the AD converter 11; and a failure detection circuit 13 that detects whether the AD converter 11 has a failure based on a correction amount by the digital assist circuit. The semiconductor device 1 is therefore able to detect the excessive variation among the elements that constitute the AD converter 11 as a failure.

A Trojan detection system places watermark circuits within an analog circuit design that allow the system to observe a node within an analog circuit under test (CUT) that is otherwise not observable. The watermark circuit can be a pass transistor logic (PTL)-based connection between the node and a readable output pin (i.e., a watermark output pin). In particular, the watermark circuits can be inserted at a node where a Trojan is likely to be inserted; thus, the watermarks provide a manner for observing changes (e.g., voltage changes) caused by a malicious modification to an analog circuit. The detection system can identify potential locations (nodes) in the CUT where a Trojan may be inserted using one or more neural networks. The detection system can then insert watermark circuits connected to the identified locations.

A Trojan detection system places watermark circuits within an analog circuit design that allow the system to observe a node within an analog circuit under test (CUT) that is otherwise not observable. The watermark circuit can be a pass transistor logic (PTL)-based connection between the node and a readable output pin (i.e., a watermark output pin). In particular, the watermark circuits can be inserted at a node where a Trojan is likely to be inserted; thus, the watermarks provide a manner for observing changes (e.g., voltage changes) caused by a malicious modification to an analog circuit. The detection system can identify potential locations (nodes) in the CUT where a Trojan may be inserted using one or more neural networks. The detection system can then insert watermark circuits connected to the identified locations.