Patent classifications
G01R31/31702
METHOD FOR DETERMINING CHARACTERISTIC PARAMETERS OF AN OSCILLATOR
A method for determining characteristic parameters of an electrostatic actuation oscillator, where the method includes generating a first excitation voltage defined as being the sum of a first sinusoidal voltage and a voltage pulse; applying the first excitation voltage at the input of the oscillator; acquiring in the time domain a first response voltage present at the output of the oscillator when the first excitation voltage is applied at the input of the oscillator; obtaining, by transformation in the frequency domain, a first amplitude spectral density of the first response voltage; determining the characteristic parameters of the oscillator from the first amplitude spectral density.
A METHOD OF PRECHARGING A SWITCHABLE FILTER
A switching or switchable filter configured to switch in and out a filter with a minimal transient, the filter comprising a capacitor charged via a voltage follower. A resistor between the capacitor and the voltage follower may be short-circuited.
Calibration method, calibration apparatus, and program
A calibration method, a calibration apparatus, and a program capable of estimating a degree of signal loss of an input signal supplied to an oscillator are provided. The calibration method includes: outputting an input signal to be input to an oscillator to be calibrated that includes a resonator and performs parametric oscillation, from a signal generator connected to the resonator via a transmission path while sweeping a frequency or a power of this input signal; acquiring distribution data of an intensity of a reflection signal based on measurement of the intensity of the reflection signal from the oscillator in response to the input signal; and estimating a degree of signal loss by comparing the distribution data acquired by the measurement with the distribution data theoretically obtained in which a value of the degree of the signal loss of the transmission path is assumed.
Method and system for creating dipole moment model
The present disclosure provides a method and system for creating dipole moment model. The method is applied to a tested circuit and includes: performing a near-field measurement on the tested circuit, to obtain a near-field electric field and a near-field magnetic field related to the tested circuit; performing a two-dimensional divergence calculation on the near-field electric field and the near-field magnetic field, to obtain a near-field electric divergence field and a near-field magnetic divergence field; performing a convolution calculation on the near-field electric divergence field and the near-field magnetic divergence field with a digital filter; and building a dipole moment matrix equivalent to the tested circuit according to a result of the convolution calculation.
Test devices, test systems, and operating methods of test systems
A test device configured to test a device under test (DUT) performing an interface of a pulse amplitude modulation (PAM) operation includes a logic generation/determination device configured to generate multiple bits corresponding to a test pattern, first and second drivers configured to generate respective first and second non return to zero (NRZ) signals according to a logic state of respective first and second bits among the multiple bits and output the respective generated first and second NRZ signals via respective first and second channels. The first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit. The first and second high levels are different from each other.
Detection of current change in an integrated circuit
An embodiment relates to an integrated circuit comprising measurement means for detection of a current change, wherein said measurement means comprise at least one coil.
Detecting a function section in a representation of a quantum circuit
A method, apparatus, and product comprising: obtaining a representation of a quantum circuit; determining that a qubit is a candidate auxiliary qubit by estimating that a state of the qubit at a first cycle is identical to a state of the qubit at a second cycle; identifying a function section in the quantum circuit based on the qubit, the function section commencing at a beginning cycle, the beginning cycle is ordered before the second cycle, the function section ending at an ending cycle, the ending cycle is ordered after the first cycle, the ending cycle is ordered after the commencing cycle, the function section utilizing the qubit as an auxiliary qubit; and outputting an indication of the function section.
Detecting a Function Section in a Representation of a Quantum Circuit
A method, apparatus, and product comprising: obtaining a representation of a quantum circuit; determining that a qubit is a candidate auxiliary qubit by estimating that a state of the qubit at a first cycle is identical to a state of the qubit at a second cycle; identifying a function section in the quantum circuit based on the qubit, the function section commencing at a beginning cycle, the beginning cycle is ordered before the second cycle, the function section ending at an ending cycle, the ending cycle is ordered after the first cycle, the ending cycle is ordered after the commencing cycle, the function section utilizing the qubit as an auxiliary qubit; and outputting an indication of the function section.
Systems and methods for on-chip noise measurements
Systems and methods for measuring noise in discrete regions of multi-layer superconducting fabrication stacks are described. Methods for measuring noise in spatial regions of a superconducting fabrication stacks may include the use of resonators, each having a different geometry. As many resonators as spatial regions are fabricated. Data collected from the resonators may be used to calculate fill fractions and spin densities for different spatial regions of the superconducting fabrication stack. The data may be collected via on-chip electron-spin resonance. The superconducting fabrications may be part of a fabrication stack for a superconducting processor, for example a quantum processor, and the spatial region studied may be proximate to qubit wiring layers.
3D integrated circuit with enhanced debugging capability
An integrated circuit includes a plurality of layers. A subset of the plurality of layers is reserved for implementing user circuitry. At least a portion of a selected layer of the plurality of layers is reserved for debugging.