The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Provided is a test apparatus for testing a device under test (DUT), the apparatus operating at an operating frequency that is lower than an operating frequency of the DUT. The test apparatus includes a clock source which generates a clock according to the operating frequency of the test apparatus, a clock multiplier configured to multiply the generated clock source by a multiplication number which is set according to the operating frequency of the DUT and output a first clock for the DUT, a phase converter configured to shift a phase of the generated clock according to the multiplication number and output a plurality of second clocks having different phases, and a test pattern comparator configured to sequentially collect pieces of data from the DUT by sequentially applying the plurality of second clocks having different phases.

A method for detecting errors of a first field-programmable gate array (FPGA) program includes: receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.

A method for testing a many-core processor comprises grouping a plurality of cores in the processor into a plurality of super cores, wherein each super core comprises one or more scan chains that propagate through a respective super core. Further, the method comprises grouping the plurality of super cores into a plurality of clusters. The method also comprises comparing one or more scan chain outputs of respective super cores in each cluster using a network of XOR and OR gates to generate a single bit fault signature for each scan chain in a respective cluster and compacting the single bit fault signatures for each scan chain using a hybrid of spatial and temporal compactors to generate a single bit fault signature for each cluster. The method also comprises method of using a cost function to obtain hierarchical parameters to achieve optimized ATPG effort, area overhead and test time.

A method of detecting leakage of a data qubit includes applying a first cross-resonance pulse to the data qubit, the data qubit including a first state and a second state; applying a first echo pulse to the data qubit temporally following the applied first cross-resonance pulse; applying a second cross-resonance pulse to the data qubit temporally following the applied first echo pulse, the second cross-resonance pulse being an inverted form of the first cross-resonance pulse; applying a second echo pulse to the data qubit temporally following the second cross-resonance pulse; and detecting a leakage associated with the data qubit using an ancilla qubit coupled to the data qubit based on application of the first and second cross-resonance pulses, and the first and second echo pulses.

A vehicle system is provided with an input pin, an interface unit and a microcontroller. The input pin connects to an external power source or ground through an external switch. The interface unit is adapted to connect to the input pin in a test configuration, and in a normal configuration for providing a wetting current to the external switch, and in a test configuration. The microcontroller is programed to: configure the interface unit in the normal configuration in response to input pin characteristics, reconfigure the interface unit in the test configuration, measure a test voltage of the interface unit, and generate output indicative of a status of the external switch based on a comparison of the test voltage to a reference voltage.

A system and method for performing speaker load diagnostics. A digital signal processor generates a diagnostic tone that is provided to the speaker. The diagnostic tone is generated using an oscillator internal to the digital signal processor. The digital signal processor receives current and voltage data from the speaker based on the diagnostic tone, and processes the current and voltage data to determine whether a fault condition exists in the speaker.

An example device includes built in test observation controller circuitry configured to: obtain a test; send first instructions to the processor to begin to execute the test by modifying values stored in a plurality of memory circuits; send second instructions to the processor to stop execution of the test at a first simulation time, wherein one or more memory values that are unobservable during a second simulation time of the test execution are observable during the first simulation time; and enhanced chip access trace scan circuitry configured to select a subset of the values from the plurality of memory circuits while the test is stopped; and signature circuitry configured to: determine a logic signature based on the subset of the values; and provide the logic signature for comparison to an expected signature, wherein a difference between the logic signature and the expected signature corresponds to a fault in the processor.

Disclosed in the present invention are a chip port state detection circuit, a chip, and a communication terminal. The chip port state detection circuit, by means of a port detection conversion circuit, converts the state of a port to be detected into a corresponding voltage and respectively outputs same to a first comparator and a second comparator, which, after comparing same with a corresponding input reference voltage, output a logic signal to a chip ID determination circuit to obtain a chip ID corresponding to the state of the chip port to be detected, in order to distinguish multiple identical chips.

An integrated circuit (IC) protection circuit can include a reconfigurable block that receives a seed value from a tamper-proof memory and generates a dynamic key; an authentication block that receives the dynamic key from the reconfigurable block and taint bits from a scan chain to generate an authentication signature; and an encryptor that encrypts a test pattern response on the scan chain if a mismatch is found between the authentication signature and a test pattern embedded signature.