The present disclosure discloses an oscillation handling method, an apparatus using the same, and a storage medium. The method includes: obtaining one of a real-time detection voltage and a real-time power of an oscillation system; reducing a gain of the system according to a preset first attenuation value; determining whether the real-time detection voltage meets a first oscillation determination condition; if yes, increase an oscillation determination number by one; restoring the gain of the system to obtain the second real-time detection voltage; determining whether the second real-time detection voltage meets a second oscillation determination condition; if yes, increase the oscillation determination number by two and reduce the gain of the system according to the preset first attenuation value; and determining the preset first attenuation value as a determined oscillation attenuation value in response to the oscillation determination number being larger than or equal to a preset threshold.

A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.

In one embodiment, a method includes: powering on an integrated circuit (IC) and causing the IC to enter into a reset mode, where in the reset mode, a switch coupled between an oscillator of the IC and a reset pin is open; releasing the reset pin to cause the IC to enter into a non-reset mode, where in the non-reset mode the switch is closed to cause the clock signal to be superimposed on a reset signal at the reset pin; and determining, via a monitoring circuit coupled to the IC, the IC as functional in response to identifying the clock signal superimposed on the reset signal at the reset pin.

An electronic circuit includes a ramp signal generator, an oscillator, a monitoring circuit and a logic controller. The ramp signal generator generates a ramp signal. The oscillator generates a clock signal. The monitoring circuit operates in an operation mode selected from a first mode of monitoring an external output voltage and a second mode of performing an analog built-in self-test (ABIST), and generates a comparator output. The logic controller controls the monitoring circuit to operate in the operation mode. When the monitoring circuit operates in the second mode, the logic controller counts the clock signal, controls the monitoring circuit to perform the ABIST based on the ramp signal, and generates an ABIST output indicating whether the monitoring circuit operates normally based on a value of the counting and the comparator output.

A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.

An electrical circuit for testing primary internal signals of an ASIC. Only test pin is provided via which a selection can be made of a digital or analog signal to be observed. The electrical circuit includes a Schmitt trigger between the test pin and an output terminal of the electrical circuit. A test mode id activated when a switching threshold of the Schmitt trigger is exceeded. At least one sub-circuit is provided for the observation of a digital signal, having a resistor, an NMOS transistor, and an AND gate, at whose first input the digital signal is present. The resistor is between the test pin and the drain terminal of the NMOS transistor. The source terminal is connected to ground, and the gate terminal is connected to the output of the AND gate. The second input of the AND gate being connected to the output terminal of the electrical circuit.

In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.

A defect detecting system of an automotive apparatus is provided. The defect detecting system includes: a digital function block including: a memory device configured to store data, and a first Built-In Self Test (BIST) configured to detect a defect of the memory device; an analog function block including a verification parity generator configured to: receive the data through a first path, generate verification parity of the data, and transmit the verification parity to the digital function block through a second path; and a level shift block connected between the digital function block and the analog function block, wherein the level shift block is configured to: convert the first path from a first power supply voltage to a first level based on a second power supply voltage, and convert the second path from the second power supply voltage to a second level based on the first power supply voltage.

The present disclosure discloses a method and an apparatus for testing an artificial intelligence chip test, a device and a storage medium, and relates to the field of artificial intelligence. The specific implementation solution is: the target artificial intelligence chip has multiple same arithmetic units, the method includes: obtaining scale information of the target artificial intelligence chip; determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information; dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a DFT test on the arithmetic unit arrays, respectively, if it is determined that the test condition of the arithmetic unit array level is satisfied; performing the DFT test on the arithmetic units, respectively, if it is not determined that the test condition of the arithmetic unit array level is not satisfied.

A method, a system, and a non-transitory computer readable medium for verifying pin name include storing information of a plurality of components of a circuit to be verified; running the circuit to be verified, and generating a components pin report of the components; comparing the components pin report and the stored information of the components, to determine whether names of pins of the components of the circuit to be verified are correct; when the components pin report and the stored information of the components are different, determining that the name of the pins of the components of the circuit to be verified is incorrect; and when the components pin report and the stored information of the components are the same, determining that the name of the pins of the components of the circuit to be verified is correct.