The present invention provides a method, device, and system for testing devices under testing (DUTs). The method comprises: sending a scan activated signal and a synchronous clock signal via the second signal line, and sending a first preset signal via the serial signal line, wherein each bit of the first preset signal is transmitted to a corresponding scan chain unit in a sequence of serial connection of the plurality of scan chain units with according to the synchronous clock signal, the corresponding scan chain unit is one of the plurality of scan chain units connected serially and coupled to the plurality of DUTs via a third signal line; sending a scan deactivated signal via the second signal line, to deactivate the scan chain units from identifying and receiving the first preset signal; and sending a second preset signal via the second signal line, and sending a test signal via the first signal line.

A computer implemented method may include executing a first simulation test for testing a device under test (DUT) and a corresponding test environment; saving a snapshot image of the DUT and of the corresponding test environment upon completion of initialization actions included in the first simulation test to configure the DUT; compiling a DUT part of a second simulation test into the saved snapshot image of the DUT to obtain a restore image for the DUT; loading the restore image of the DUT and restoring the snapshot image of the test environment; loading a test environment part of the second simulation test; and executing the second simulation test on the DUT and corresponding test environment.

A testing device includes a transmitter circuit, a receiver circuit, and a loopback circuit. The transmitter circuit is configured to receive a plurality of first test signals. The receiver circuit is configured to receive input data from a plurality of pads in a normal mode. The loopback circuit is coupled to the plurality of pads and input terminals of a sampler circuit, and the loopback circuit is configured to transmit the plurality of first test signals from the transmitter circuit to the input terminals of the sampler circuit, in order to generate test data for subsequent analysis.

An integrated circuit (IC) includes: a first functional analog pin or pad; a first analog test bus coupled to the first functional analog pin or pad; first and second analog circuits coupled to the first analog test bus; and a test controller configured to: when the IC is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus so that the input or output of the first analog circuit is accessible by the first functional analog pin or pad, and keep disconnected an input or output of the second analog circuit from the first analog test bus, and when the IC is in a test mode, selectively connect the input or output of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus.

A method for detecting errors of a first field-programmable gate array (FPGA) program includes: receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.

A scan flip-flop includes a multiplexer, a first latch, a second latch, an output buffer and a clock buffer. The multiplexer selects one of a data input signal and a scan input signal based on an operation mode. The first latch latches an output of the multiplexer. The second latch latches an output of the first latch. The output buffer generates an output signal based on an output of the second latch. The clock buffer generates a first clock signal and a second clock signal that control operation of the first latch and the second latch. The first latch, the second latch, and the clock buffer are sequentially arranged along a first direction. A first clock line supplying the first clock signal and a second clock line supplying the second clock signal have a cross couple connection.

A method for managing transactions burstiness associated with a sequence of transactions generated in a test environment for verifying a Device Under Test (DUT) is disclosed. In some embodiments, the method includes processing a plurality of signals associated with a sequence of transactions. The method further includes generating a transactions burstiness signature representative of the sequence of transactions based on processing a set of signals from the plurality of signals. The method further includes analysing the transactions burstiness signature to identify at least one pattern of interest. The method further includes iteratively providing an input comprising at least one missing pattern of interest. The method further includes iteratively generating a subsequent sequence of transactions and a subsequent transactions burstiness signature associated with the subsequent sequence of transactions.

A method for checking a Design for Test (DFT) circuit includes: transmitting a control signal to the DFT circuit to determine test mode signals output by the DFT circuit, with the DFT circuit being configured to sequentially select multiple address latches according to the control signal to output the test mode signals; analyzing the test mode signals to determine whether the multiple address latches in the DFT circuit have an error; and outputting a simulation result report.

The present disclosure discloses a method and an apparatus for testing an artificial intelligence chip test, a device and a storage medium, and relates to the field of artificial intelligence. The specific implementation solution is: the target artificial intelligence chip has multiple same arithmetic units, the method includes: obtaining scale information of the target artificial intelligence chip; determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information; dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a DFT test on the arithmetic unit arrays, respectively, if it is determined that the test condition of the arithmetic unit array level is satisfied; performing the DFT test on the arithmetic units, respectively, if it is not determined that the test condition of the arithmetic unit array level is not satisfied.

A method, a system, and a non-transitory computer readable medium for verifying pin name include storing information of a plurality of components of a circuit to be verified; running the circuit to be verified, and generating a components pin report of the components; comparing the components pin report and the stored information of the components, to determine whether names of pins of the components of the circuit to be verified are correct; when the components pin report and the stored information of the components are different, determining that the name of the pins of the components of the circuit to be verified is incorrect; and when the components pin report and the stored information of the components are the same, determining that the name of the pins of the components of the circuit to be verified is correct.