An embodiment herein provides a method for implementing verification IP for pre-silicon functional verification of a layered protocol. The method includes generating serially connected layer blocks. A layer block includes modular components that may be enabled or disabled to change a functionality of the layer block. The modular components include a layer core, a stimulus handler, one or more transmit routers and one or more receive routers. The layer core implements the complete functionality of the layer block. The stimulus handler drives input stimulus transactions into the layer core of the layer block. The one or more transmit routers routes one or more transmit core transactions from the layer core to the connected succeeding layer block. The one or more receive routers routes one or more receive core transactions from the succeeding layer block to the layer core.

A digital circuit robustness verification method is provided that includes the following steps. An internal storage circuit and an external storage circuit corresponding to a circuit under test are set to store a plurality of random values and a configuration of the circuit under test for performing a predetermined function is set by a processing circuit. A driving signal corresponding to the predetermined function is transmitted to the circuit under test by a previous stage circuit, such that the circuit under test executes the predetermined function to further generate an output signal. The determination as to whether the output signal is correct or not is made by a next stage circuit, and the circuit under test is determined to pass a robustness verification when the output signal is correct.

A scan cell comprises: a state element and selection and combination circuitry. The selection and combination circuitry comprises first combination circuitry configured to combine a signal from a scan input of the scan cell with a signal from a functional circuit input of the scan cell to generate a first signal, second combination circuitry configured to combine the signal from the functional circuit input of the scan cell with an output signal of the state element to generate a second signal, and selection circuitry configured to select an input signal for the state element from the signal from the scan input of the scan cell, the signal from the functional circuit input of the scan cell, the first signal, and the second signal based on two selection input signals of the scan cell.

An integrated circuit includes first and second cores. Each core has a power-switchable portion in a first power domain in which an operating power is turned on or off in response to a power control signal. The first power domain includes a first scan chain, and the first power domain also includes a plurality of outputs. Each core also includes an always-on portion in a second power domain in which the operating power is maintained during testing of the integrated circuit. The second power domain also has a second scan chain. The second power domain further includes respective isolation gates coupled to the plurality of outputs of the first power domain, and the second scan chain includes a respective wrapper cell coupled to some isolation gates. The integrated circuit is configured to power off and isolate the power-switchable portion in the first power domain based on a scan test result.

A method and a system for verifying an integrated circuit stack having at least one silicon photonic device is introduced. A dummy layer and a dummy layer text are added to a terminal of at least one silicon photonic device of the integrated circuit. The method may perform a layout versus schematic check of the integrated circuit including the dummy layer and the dummy layer text.

Methods and design system for generating 2-dimensional distribution architecture for testing integrated circuit design that utilizes double grid to minimize interdependencies between grid cells and the associated functional logic to facilitate the a physically efficient scan of integrated circuit designs, that simultaneously minimizes required test application time (TAT), test data volume, tester memory and cost associated with design for test (DFT), while also retaining test coverage. An additional grid parallel to a 2-dimensional XOR grid may be implemented that improves the quality of test coverage by optimally adding additional data inputs which decreases correlations between grid cells. A column spreader may feed data into column wires and row spreader may feed data into column wires. The double grid allows data to be fed into two wires, row and column, respectively, which provides twice as much stimulus data in each direction, without significantly increasing the wiring used to build the grid.

A computer system includes a hardware accelerator and host processor. The hardware accelerator executes a simulation of a first logical model according to a plurality of simulation cycles. The host processor determines a fault checkpoint based on a logic fault that occurs in response to executing the simulation. The host processor verifies removal of the logic fault based on rerunning the simulation from the fault checkpoint.

Design-for-test (DFT) architectures, and methods of testing an array of chips, which may be identical, are described. In an embodiment, a comparison circuit includes a plurality of comparators to compare scan-data out (SDO) data streams with an expected data stream and transmit a compared data stream that is indicated of whether or not an error exists in any of the SDO data streams.

One embodiment provides a method and a system for computing diagnoses for a physical system. During operation, the system can obtain a design of the physical system, generate a design of a diagnostic system by augmenting the design of the physical system based on a number of fault-emulating subsystems, and convert the design of the diagnostic system into a polynomial formula comprising a plurality of variables. The plurality of variables can include inputs and outputs of the original physical system and a number of ancillary variables. The system can further embed the polynomial formula on a hardware-based solver configured to perform optimization using the polynomial formula as an objective function to obtain a diagnostic vector used for explaining faults in the physical system.

An embodiment herein provides a method for implementing verification IP for pre-silicon functional verification of a layered protocol. The method includes generating serially connected layer blocks. A layer block includes modular components that may be enabled or disabled to change a functionality of the layer block. The modular components include a layer core, a stimulus handler, one or more transmit routers and one or more receive routers. The layer core implements the complete functionality of the layer block. The stimulus handler drives input stimulus transactions into the layer core of the layer block. The one or more transmit routers routes one or more transmit core transactions from the layer core to the connected succeeding layer block. The one or more receive routers routes one or more receive core transactions from the succeeding layer block to the layer core.