An apparatus includes an event message generator configured to generate an event message. The apparatus further includes a filter circuit configured to receive the event message and to send a first portion of the event message to a destination device. The filter circuit is further configured to selectively send a second portion of the event message to the destination device at least partially based on an event traffic load associated with the destination device.

Embodiments of the invention include methods, systems and devices for implementing the auto detection of Joint Test Action Group (JTAG) debuggers/emulators. Embodiments include sending a reset signal to reset one or more slave devices, and detecting a programming signal indicating the one or more slave devices are in a programming/debugging mode. Embodiments also include responsive to the signal, inhibiting resetting one or more slave devices receiving the programming signal.

A circuit is for coupling test access port (TAP) signals to a Joint Test Action Group (JTAG) interface in an integrated circuit package. An nTRST pin receives a test reset signal, a TMS pin receives a test mode select signal, a testing test access port (TAP) has a test reset signal input and a test mode select signal input, and a debugging test access port (TAP) has a test reset signal input coupled to the nTRST pin and a test mode select signal input coupled to the TMS pin. An inverter has an input coupled to the nTRST pin and an output coupled to the test reset signal input of the testing TAP, and an AND gate has a first input coupled to the output of the inverter, a second input coupled to the TMS pin, and an output coupled to the test mode select input of the testing TAP.

Systems and methods for secure testing and debugging of electronic devices are described. In one embodiment, the systems and methods may include an electronic device that includes a control switch placed on a device test bus of the electronic device between a debugger external to the device and a debug interface on the device. In some cases, the device may include at least one register placed on the device test bus between the debugger and authentication logic of the electronic device.

A method of reconfiguring a current debug configuration of a debug unit connected to a peripheral circuit on an integrated circuit chip. The method comprises the debug unit collecting debug data of the peripheral circuit and outputting the debug data in a message stream. The debug unit receives a debug reconfiguration command. The debug unit transmits an indication of the current debug configuration, then reconfigures the current debug configuration to a new debug configuration in accordance with the debug reconfiguration command, then transmits an indication of the new debug configuration. The indication of the current debug configuration and the indication of the new debug configuration are transmitted adjacent to the debug data in the message stream.

A method for monitoring a communication link between a device under test (DUT) and automated test equipment is disclosed. The method comprises monitoring data traffic associated with testing a DUT using a protocol analyzer module, wherein the data traffic comprises a flow of traffic between the DUT and a protocol core of a programmable logic device, wherein the protocol analyzer module is integrated within the programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test the DUT, and wherein the protocol core is operable to generate signals to communicate with the DUT using a protocol associated with the DUT. The method further comprises saving results associated with the monitoring in a memory associated with the protocol analyzer module and transmitting the results upon request to an application program executing on the system controller.

Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a debug and test access port to debug and test the device circuit, and a switching circuit to switch a debug and test mastership between the debug and test access port and a data access port to the device circuit that is not dedicated to debug and test.

An electronic device includes one or more integrated circuits, a debugging translation block, and a bus connected to the one or more integrated circuits and the debugging translation block, the bus configured to provide a connection to one or more external devices, wherein the debugging translation block is configured to receive debugging commands from a testing host device via the bus, convert the debugging commands into debugging input data, and provide the debugging input data to a debugging state machine of a first integrated circuit of the one or more integrated circuits.

The invention discloses an interface system for an interconnected die and an MPU and a communication method thereof. The system comprises a data interface, an interrupt interface, and a debugging interface; the data interface comprises an SPI interface, a DDR data interface, and a DMA control interface; the interrupt interface is used for receiving an interrupt data packet from the network and parsing the interrupt data packet to obtain a pulse interrupt input required by the MPU; the debugging interface comprises a JTAG-Core debugging interface, which is used for receiving a debugging data packet from the network and translating the debugging data packet into a JTAG protocol for MPU debugging. The invention realizes the expansion of the master device MPU in the high-performance information processing microsystem and the high-speed communication between the master device and the interconnected dies.

A method for analyzing a simulation of the execution of a quantum circuit comprises: a step of post-selecting (S2) one or more particular values of one or more qubits at one or more steps of the simulation, a step of retrieving (S5), by an iterator (7), all or some of the quantum states of the quantum state vector(s) derived from the post-selection(s) of qubits, a step of analyzing (S6) the part of the simulation that corresponds to the post-selection(s) of qubits and to the quantum state vector(s) retrieved.