A processor includes a transmitter to transmit, to a receiver, a differential pair of signals including a positive signal transmitted across a positive conductor and a negative signal transmitted across a negative conductor. A first programmable analog delay circuit is coupled to the positive conductor to provide a first delay to the positive signal and a second programmable analog delay circuit is coupled to the negative conductor to provide a second delay to the negative signal. A controller receives data based on a bit error rate (BER) of the differential pair of signals as measured by a bit error checker of the receiver. In response to determining the BER is less than a threshold BER, the controller stores a first delay value to program the first delay and store a second delay value to program the second delay.

The present disclosure provides a differential clock cross point detection circuit and a detection method. The detection circuit includes: a first MOS transistor (M1), a second MOS transistor (M2) and a capacitor (C); a drain of the first MOS transistor (M1) is connected to a negative terminal (CLK−) of a differential clock, a gate of the first MOS transistor (M1) is connected to a positive terminal (CLK+) of the differential clock, and a source of the first MOS transistor (M1) is connected to a drain of the second MOS transistor (M2); a gate of the second MOS transistor (M2) is connected to the negative terminal (CLK−) of the differential clock, and a source of the second MOS transistor (M2) is connected to an output terminal through a node; one terminal of the capacitor (C) is connected to a node (A), and the other terminal of the capacitor (C) is grounded.

An apparatus may comprise a skew detection circuit to sample a common mode voltage of a differential signal, wherein the sampled common mode voltage is indicative of an amount of skew between a first signal of the differential signal and a second signal of the differential signal; and a skew compensation circuit to adjust a delay of the first signal or the second signal based on the sampled common mode voltage to reduce the amount of skew.

Systems, methods, and computer readable medium described herein relate to techniques for characterizing and/or anomaly detection in integrated circuits such as, but not limited to, field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). In one example aspect of certain example embodiments, a fully digital technique relies on the pulse width of signals propagated through a path under test. In another example aspect, the re-configurability of the integrated circuit is leveraged to combine the pulse propagation technique with a delay characterization technique to yield better detection of certain type of Trojans and the like. Another example aspect provides for running the test through reconfigurable path segments in order to isolate and identify anomalous circuit elements. Yet another example aspect provides for performing the characterization and anomaly detection without requiring golden references and the like.

Scan-chain testing of a semiconductor chip may be performed entirely via a deserializer port. In one illustrative device embodiment, a semiconductor chip includes at least one deserializer having: a serial-to-parallel converter coupled to a pair of differential signal input pins; a scan-chain receiver circuit coupled to at least one of the pair of differential signal input pins in parallel with the serial-to-parallel converter to receive a scan-chain test input data stream; a scan-chain test logic circuit that loads the scan-chain test input data stream into a scan chain and extracts a scan-chain test result data stream from the scan chain; and a scan-chain transmit circuit that drives the pair of differential signal input pins with the scan-chain test result data stream. If multiple SerDes blocks exist on the chip, the deserializer ports may be employed in parallel for input and output of test data streams.

A device includes a comparator, a reference signal node, a plurality of test signal nodes, and control logic. The reference signal node receives a reference signal. The reference signal node is coupled to a first input of the comparator. Each of the plurality of test signal nodes receives a corresponding test signal. The control logic is configured to initiate a comparison of each test signal to the reference signal via the comparator.

Methods and systems are provided for testing and/or programming a thread-type string of RFID tags or devices. A thread-type RFID tag is formed on a length or thread having an RFID chip, a first antenna section and a second antenna section, the first and second antenna sections being positioned on the length of thread on opposite sides of the RFID chip. An RFID reader is positioned in electronic communication with a first coupler and a second coupler lying along a path, and the RFID tag and couplers are in relative motion with respect to each other such that the first and second couplers are on opposite sides of the RFID chip. A differential electric field is applied between the first coupler and the second coupler and across the RFID chip whereby the RFID reader couples to the RFID chip and interacts with the RFID tag to carry out testing and/or programming tasks with respect to the RFID tag.

A backplane testing system is provided. Based on the connection relationship and signal transfer relationship of a differential signal transceiver, a backplane and a loop device, the differential signal transceiver generates a set of pseudo random binary sequence (PRBS) as a differential signal, and sends the differential signal and receives the returned differential signal, and then determines whether the differential signals sent and received are the same; and the differential signal transceiver generates a test signal that conforms to the IEEE-1149.6 boundary scan test standard, and sends the test signal and receives the returned test signal through a second positive differential signal circuit and a second negative differential signal circuit, and then determines whether the test signals sent and received through the second positive differential signal circuit are the same and whether the test signals sent and received through the second negative differential signal circuit are the same.

A test and measurement system including a plurality of channels and one or more processors. The one or more processors are configured to cause the test and measurement system to receive, via a first channel of the plurality of channels, a positive side of a reference differential signal pair, receive, via a second channel of the plurality of channels, a negative side of the reference differential signal pair, and produce a reference signal based the reference differential signal pair. A combined signal is received, from a combiner, that is a balanced signal produced from the reference differential signal pair. A de-embed filter is generated based on the reference signal and the combined signal and an additional signal is received from the combiner and an effect of the combiner is removed from the additional signal by applying the de-embed filter to the additional signal.

A differential signal measurement system is provided. The differential signal measurement system includes a measurement device, with at least one differential signal input, a differential connection interface configured to connect the at least one differential signal input of the measurement device to a device under test, and a differential signal source, with at least one differential signal output, configured to generate at least one differential output signal. The differential connection interface is further configured to pass the at least one differential output signal to the at least one differential signal input of the measurement device, and the measurement device is configured to capture the at least one differential output signal.