A differential voltage measuring device includes a first capacitor and a second capacitor each formed of a ceramic capacitor, a differential amplifier for outputting a voltage corresponding to a difference voltage between a voltage held by the first capacitor and a voltage held by the second capacitor, and COM for introducing a first voltage to the first capacitor, and a second voltage to the second capacitor with the first capacitor holding the first voltage, and COM introduces a third voltage to at least the first capacitor or the second capacitor, and after application of the third voltage stops, introduces the first voltage to the first capacitor or the second capacitor to which the third voltage was introduced.

Systems, methods, and computer readable medium described herein relate to techniques for characterizing and/or anomaly detection in integrated circuits such as, but not limited to, field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). In one example aspect of certain example embodiments, a fully digital technique relies on the pulse width of signals propagated through a path under test. In another example aspect, the re-configurability of the integrated circuit is leveraged to combine the pulse propagation technique with a delay characterization technique to yield better detection of certain type of Trojans and the like. Another example aspect provides for running the test through reconfigurable path segments in order to isolate and identify anomalous circuit elements. Yet another example aspect provides for performing the characterization and anomaly detection without requiring golden references and the like.

Aspects of the present disclosure are directed to assessing integrity of communications circuitry. As may be implemented in accordance with one or more embodiments, a circuit node carries out a test protocol utilizing characteristics of a communication protocol to detect potential integrity issues. An initial test bit sequence is transmitted to circuit nodes connected to signal lines of a bus, by providing a test voltage across the signal lines that is less than an operating voltage potential of the bus. An ensuing state of the bus is sensed, and integrity of the bus or of circuitry connected to the bus is assessed based on the sensed state of the bus and on a state that the bus is expected to be in after transmission of the initial test bit sequence, which is used as an indication of whether all of the circuit nodes received the initial test bit sequence.

Embodiments of the present application disclose a method and a device of detecting a low voltage differential signal output to a liquid crystal display panel. In the method, the low voltage differential signal is decoded into a pixel color data signal; and then blanking signals of the pixel color data signal are counted.

A device includes a comparator, a reference signal node, a plurality of test signal nodes, and control logic. The reference signal node receives a reference signal. The reference signal node is coupled to a first input of the comparator. Each of the plurality of test signal nodes receives a corresponding test signal. The control logic is configured to initiate a comparison of each test signal to the reference signal via the comparator.

The present invention has a first step for inputting an inspection signal having a predetermined pattern simultaneously to a plurality of devices connected in parallel to a tester and starting inspection having a predetermined pattern, a second step for determining whether a non-passing device is included in the predetermined pattern, a third step for sequentially executing a predetermined pattern and determining passing/non-passing (PASS/FAIL) status for each of the plurality of devices when it is determined in the second step that a non-passing device is included, and a fourth step for excluding a device determined as non-passing in the third step, subsequent inspection being performed for the devices other than the excluded device.

A signal correction method for correcting a measured signal has the following steps: processing a digital representation of a first signal at a first measurement input; processing a digital representation of a second signal at a second measurement input corresponding to the first signal convoluted with a transfer function; and determining the transfer function for correcting the measured signal. Further, a use of the method, a system for correcting a measured signal, and an oscilloscope are provided.

A device includes a comparator, a reference signal node electrically coupled to a first input of the comparator, a plurality of test signal nodes, a plurality of first select signal nodes, a first multiplexer coupled between the plurality of test signal nodes and the comparator, a plurality of latches, a plurality of second select signal nodes, and a second multiplexer. Each first select signal node corresponds to a test signal node. The first multiplexer electrically couples one of the plurality of test signal nodes to a second input of the comparator in response to a corresponding first select signal. Each latch corresponds to a test signal node. Each second select signal node corresponds to a latch. The second multiplexer electrically couples the output of the comparator to an input of one of the plurality of latches in response to a corresponding second select signal.

A device includes a comparator, a reference signal node electrically coupled to a first input of the comparator, a plurality of test signal nodes, a plurality of first select signal nodes, a first multiplexer coupled between the plurality of test signal nodes and the comparator, a plurality of latches, a plurality of second select signal nodes, and a second multiplexer coupled between an output of the comparator and the plurality of latches. Each first select signal node corresponds to a test signal node. The first multiplexer electrically couples one of the plurality of test signal nodes to a second input of the comparator in response to a corresponding first select signal. Each latch corresponds to a test signal node. Each second select signal node corresponds to a latch. The second multiplexer electrically couples the output of the comparator to an input of one of the plurality of latches in response to a corresponding second select signal.

Scan-chain testing of a semiconductor chip may be performed entirely via a deserializer port. In one illustrative device embodiment, a semiconductor chip includes at least one deserializer having: a serial-to-parallel converter coupled to a pair of differential signal input pins; a scan-chain receiver circuit coupled to at least one of the pair of differential signal input pins in parallel with the serial-to-parallel converter to receive a scan-chain test input data stream; a scan-chain test logic circuit that loads the scan-chain test input data stream into a scan chain and extracts a scan-chain test result data stream from the scan chain; and a scan-chain transmit circuit that drives the pair of differential signal input pins with the scan-chain test result data stream. If multiple SerDes blocks exist on the chip, the deserializer ports may be employed in parallel for input and output of test data streams.