A method for testing systems on a chip during manufacture obtains basic function information of intellectual property cores and relevant information of network on chip and generates one or more test names according to the basic function information, and the relevant information of the network on chip. The method invokes a pre-prepared integral script to construct a running environment configured to invoke basic function scripts of to-be-tested intellectual property cores one by one, according to each of the test names which are generated. The method also generates the results of testing. A related electronic device and a non-transitory storage medium are also disclosed.

A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.

An electronic device test database generating method, comprising: (a) acquiring cell layout information of a target electronic device; (b) generating possible defect location information of the target electronic device according to the cell layout information, wherein the possible defect location information comprises at least one possible defect location of the target electronic device; (c) testing the target electronic device according to the possible defect location information to generate a testing result; and (d) generating an electronic device test database according to the testing result.

A computer-implemented method for implementing electronic control unit (ECU) testing optimization includes capturing, within a neural network model, input-output relationships of a plurality of ECUs operatively coupled to a controller area network (CAN) bus within a CAN bus framework, including generating the neural network model by pruning a fully-connected neural network model based on comparisons of maximum values of neuron weights to a threshold, reducing signal connections of a plurality of collected input signals and a plurality of collected output signals based on connection weight importance, ranking importance of the plurality of collected input signals based on the neural network model, generating, based on the ranking, a test case execution sequence for testing a system including the plurality of ECUs to identify flaws in the system, and initiating the test case execution sequence for testing the system.

A method for testing semiconductor devices is disclosed, which includes: obtaining a result measured on a semiconductor device in one of a set of tests; comparing the result with a maximum value determined among respective results that were previously measured in one or more of the set of tests and a minimum value determined among respective results that were previously measured in one or more of the set of tests; determining, based on the comparison between the first result and the maximum and minimum values, whether to update the maximum and minimum values to calculate a delta value; comparing the delta value with a noise threshold value; determining based on the comparison between the delta value and the noise threshold value, whether to update a value of a timer; determining that the value of the timer satisfies a timer threshold; and determining that the semiconductor device incurs noise.

An electronic circuit includes a ramp signal generator, an oscillator, a monitoring circuit and a logic controller. The ramp signal generator generates a ramp signal. The oscillator generates a clock signal. The monitoring circuit operates in an operation mode selected from a first mode of monitoring an external output voltage and a second mode of performing an analog built-in self-test (ABIST), and generates a comparator output. The logic controller controls the monitoring circuit to operate in the operation mode. When the monitoring circuit operates in the second mode, the logic controller counts the clock signal, controls the monitoring circuit to perform the ABIST based on the ramp signal, and generates an ABIST output indicating whether the monitoring circuit operates normally based on a value of the counting and the comparator output.

A system and method are disclosed for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.

Methods and systems for performing fault injection testing on an integrated circuit hardware design. The methods include: (a) receiving a raw fault node list identifying one or more fault nodes of the hardware design; (b) receiving information indicating a grouping of the fault nodes in the raw fault node list into a plurality of fault node groups, each fault node group comprising fault nodes that have a same effect on a failure mode of the hardware design; (c) generating a final fault node list based on the fault node groups; (d) selecting a set of fault injection parameters from the final fault node list, the set of fault injection parameters identifying at least one fault node in the final fault node list to fault; (e) performing a fault injection test on the hardware design by causing a fault to be injected into a simulation of the hardware design based on the selected set of fault injection parameters; (f) determining a result of the fault injection test; (g) storing the result of the fault injection test; and repeating (d) to (g) at least once.

A failure detector circuit of one embodiment acquires a first signal while transmitted from a first circuit to a second circuit and acquires a second signal while transmitted from the second circuit to a third circuit. The second circuit is located between the first circuit and the third circuit and transmits, to the third circuit, as the second signal, the first signal or a third signal having a given fixed state. The failure detector circuit outputs a fourth signal indicating detection or non-detection of a failure in the second circuit, in accordance with the first signal and the second signal.

Embodiments of the disclosure provide a method and device for testing an integrated circuit (IC). Calibration parameters of test boards are determined respectively by acquiring identification information of the test boards, and then each of to-be-tested devices in each of the test boards is tested respectively based on the calibration parameters of the test boards. According to the embodiments of the disclosure, the calibration parameters of the test boards are determined respectively according to the identification information corresponding to the test boards, therefore when different types of test boards are adopted by a test machine, each type of test boards may acquire the accurate calibration parameter, so that the accuracy of a test result is ensured, the mixed test of multiple types of test boards is implemented, furthermore, the test efficiency is improved and the test cost is reduced.