A computer-implemented method for implementing electronic control unit (ECU) testing optimization includes capturing, within a neural network model, input-output relationships of a plurality of ECUs operatively coupled to a controller area network (CAN) bus within a CAN bus framework, including generating the neural network model by pruning a fully-connected neural network model based on comparisons of maximum values of neuron weights to a threshold, reducing signal connections of a plurality of collected input signals and a plurality of collected output signals based on connection weight importance, ranking importance of the plurality of collected input signals based on the neural network model, generating, based on the ranking, a test case execution sequence for testing a system including the plurality of ECUs to identify flaws in the system, and initiating the test case execution sequence for testing the system.

Systems and methods for predicting the trajectory of an object are disclosed herein. One embodiment receives sensor data that includes a location of the object in an environment of the object; accesses a location-specific latent map, the location-specific latent map having been learned together with a neural-network-based trajectory predictor during a training phase, wherein the neural-network-based trajectory predictor is deployed in a robot; inputs, to the neural-network-based trajectory predictor, the location of the object and the location-specific latent map, the location-specific latent map providing, to the neural-network-based trajectory predictor, a set of location-specific biases regarding the environment of the object; and outputs, from the neural-network-based trajectory predictor, a predicted trajectory of the object.

Methods and design system for generating 2-dimensional distribution architecture for testing integrated circuit design that utilizes double grid to minimize interdependencies between grid cells and the associated functional logic to facilitate the a physically efficient scan of integrated circuit designs, that simultaneously minimizes required test application time (TAT), test data volume, tester memory and cost associated with design for test (DFT), while also retaining test coverage. An additional grid parallel to a 2-dimensional XOR grid may be implemented that improves the quality of test coverage by optimally adding additional data inputs which decreases correlations between grid cells. A column spreader may feed data into column wires and row spreader may feed data into column wires. The double grid allows data to be fed into two wires, row and column, respectively, which provides twice as much stimulus data in each direction, without significantly increasing the wiring used to build the grid.

Methods, systems, and devices for testing a die using a segmented digital die ring are described. A segmented digital die ring may include multiple signal line segments, each coupled with a test segment circuit, and a control circuit. A test segment circuit may generate a digital feedback signal that indicates a condition of a respective signal line segment. The control circuit may generate a single output signal, indicative of the condition of the signal line segments. By utilizing digital testing circuitry and a single digital output signal, a layout area of the segmented digital die ring be minimized and a power consumption associated with the testing operation may be reduced.

Disclosed is a capability test method based on a joint test support platform. The method includes steps of describing an initial capability in a test, combining a capability to be developed based on the initial capability, and determining an evaluation strategy and a joint task background information of the test. Further, the method includes generating a logical shooting range for the joint test support platform according to the joint task background information, developing a test scenario according to the joint task background information and the logical shooting range, decomposing the test scenario, determining a test plan corresponding to the test scenario, executing the test according to the test plan, analyzing and evaluating a test result of the test, and generating one or more joint capability evaluation reports for the test.

A system can include one or more processors and computer-readable instructions that when executed by the one or more processors, cause the one or more processors to provide a first test signal to an electronic device, monitor at least one parameter of the electronic device during a time period subsequent to the test signal being provided to the electronic device, determine, based on the at least one parameter, a detected response of the electronic device to the first test signal, determine, using a response model, an expected response of the electronic device to the first test signal, and provide a second test signal based on the detected response and the expected response to the electronic device. The system can include a communications circuit that provides the test signal and receives at least some feedback indicating the parameters, and sensors that receive at least some feedback indicating the parameters.

A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.

An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

A test and measurement system for parallel waveform analysis acquires waveforms resulting from performing tests on a device under test (DUT) and performs, at least partially in parallel, respective analyses of the waveforms resulting from performing tests on the DUT. The system also acquires a first waveform resulting from performing a first test with an oscilloscope on a DUT and performs analysis of the first waveform at least partially in parallel with acquiring a second waveform. Additionally, the system tracks a plurality of testing assets using inventory information of a plurality of testing equipment on the network and enables remote users to access equipment logs and results of the respective analyses of the waveforms stored on a cloud computing system for performance of analytics.

A method for testing a multi-core integrated circuit device including a plurality of processing cores includes testing a first processing core on the integrated circuit device utilizing one or more tests. If a first feature on the first processing core fails a first test, the method includes performing a second test on the first processing core that tests the first processing core without the first feature. The method includes determining, based on the second test, if the first processing core is operable without the first feature. If the first processing core is operable without the first feature, the method includes storing information about the first processing core's capabilities in vital product data.