The disclosure relates to apparatus and methods for self-testing of a duty cycle detector. Example embodiments include a circuit (201) comprising: a clock signal generator (205) configured to provide an output clock signal (203) having a duty cycle; a duty cycle detector (208) arranged to receive the output clock signal (203) and provide an output flag if the duty cycle of the clock signal (203) is outside a predetermined range; a controller (214) arranged to provide a duty cycle select signal (216) to the clock signal generator (205) to cause the clock signal (203) to have a duty cycle outside the predetermined range and to receive the output flag to confirm operation of the duty cycle detector (208).

A system to classify signals includes an input to receive incoming waveform data; a memory, and one or more processors configured to execute code to cause the one or more processors to: generate a ramp sweep signal from the incoming waveform data, locate a data burst in the incoming waveform data using a burst detector, receive a signal from the burst detector to cause the memory to store cyclic loop image data in the form of the incoming waveform data as y-axis data and the ramp sweep signal as x-axis data, and employ a machine learning system to receive the cyclic loop image data and classify the data burst. A method of classifying signals includes generating a ramp sweep signal from incoming waveform data, locating a data burst in the incoming waveform data, storing cyclic loop image data for the data burst in the form of the incoming waveform data as Y-axis data and the ramp sweep signal as X-axis data, and using a machine learning system to receive the cyclic loop image and classify the data burst.

A switching activity report of simulated switching activities of a semiconductor circuit is accessed. A plurality of glitch bottleneck ratios corresponding to a plurality of pins in the semiconductor circuit are determined, comprising by: setting an initial bottleneck ratio on a leaf output pin; and backward traversing the semiconductor circuit to determine a plurality of glitch bottleneck ratios of pins in a fan-in cone of the leaf output pin.

A plurality of total glitch powers associated with the plurality of pins is determined, a total glitch power of the plurality of total glitch powers being determined based on a glitch bottleneck ratio and a glitch power of a corresponding pin. One or more critical bottleneck pins among the plurality of pins are identified based on the plurality of total glitch powers. One or more gates associated with the one or more critical bottleneck pins are adjusted to reduce corresponding one or more total glitch powers of the one or more gates.

The invention discloses a test method for high-speed signal frequency measurement and signal integrity. Through the combination of integrated circuit digital-analog test system and programmable digital system, the trigger signal of the test system is synchronized with the digital signal of the peripheral test circuit to generate 100 M square wave and data to verify whether the chip can work normally. When the enabling signals of the integrated circuit digital-analog test system are detected by the peripheral test circuit, the corresponding square wave signal of 100 M or the preset data signal are given to the tested digital chip. The two enabling signals have the same priority, and then sample the output of the tested digital chip, wherein, the collected output waveform needs to be logically calculated and divided into a 10 M square wave, and the frequency measurement is carried out, then the processed results are returned to the test system. The test system accurately selects the chip with correct function according to the data, and eliminates the chip with abnormal work.

A method is provided for testing discrete output signals of a device-under-test (DUT). The method includes receiving an electrical quantity at each conductive path of a plurality of conductive paths that are each coupled to respective discrete output signals of the DUT in one-to-one correspondence. The method further includes controlling application of the electrical quantity to each of the conductive path independent of application of the electrical quantity along the other conductive paths, so that a the electrical quantity is applied simultaneously to all of the conductive paths, the electrical quantity applied to each conductive path being toggled at a unique frequency having a unique period. Accordingly, a characteristic of the electrical quantity at each of the respective test output conductors over the duration of the longest period of the unique periods is indicative of any disturbance between the discrete output signals associated with the test output conductor and all of the other discrete output signals.

A signal analysis method is disclosed. The method comprises the following steps: An input signal comprising a symbol sequence is received, wherein the input signal is associated with a first clock signal comprising at least one jitter component. A second clock signal is recovered based on said input signal. At least one jitter parameter is determined that is associated with said at least one jitter component. A jitter signal is reconstructed based on said at least one jitter parameter, wherein said jitter signal is associated with said at least one jitter component. A third clock signal is determined based on said second clock signal and said jitter signal. Further, a measurement instrument is disclosed.

A margin testing device includes at least one interface structured to connect to a device under test (DUT) one or more controllers structured to create a set of test signals based on a sequence of pseudo random data and one or more pre-defined parameters, and an output structured to send the set of test signals to the DUT. Methods and a system for testing a DUT with the disclosed margin tester and other testing device are also described.

A glitch detection circuit includes a first P-type field-effect transistor and a second P-type field-effect transistor which are biased by the same current, and a channel width-to-length ratio of the first P-type field-effect transistor is higher than that of the second P-type field-effect transistor. A capacitor having a terminal grounded and another terminal connected to the gates of the first and second P-type field-effect transistors and a power supply terminal. A determination circuit configured to determine that a negative glitch occurs when a voltage decreasing amount of the drain of the first P-type field-effect transistor is greater than that of the second P-type field-effect transistor, and determine that a positive glitch occurs when an voltage increasing amount of the drain of the second P-type field-effect transistor is greater than that of the first P-type field-effect transistor.

Semiconductor devices that include test circuitry to measure internal signal wire propagation delays during memory access operations, and circuity configured to store delay information that is used to configure internal delays based on the measured internal signal propagation circuit delays. The semiconductor device includes a test circuit configured to measure a signal propagation delay between a command decoder and a bank logic circuit based on time between receipt of a test command signal directly from the command decoder and a time of receipt of the test command signal routed through the bank logic circuit.

The present disclosure discloses an oscillation handling method, an apparatus using the same, and a storage medium. The method includes: obtaining one of a real-time detection voltage and a real-time power of an oscillation system; reducing a gain of the system according to a preset first attenuation value; determining whether the real-time detection voltage meets a first oscillation determination condition; if yes, increase an oscillation determination number by one; restoring the gain of the system to obtain the second real-time detection voltage; determining whether the second real-time detection voltage meets a second oscillation determination condition; if yes, increase the oscillation determination number by two and reduce the gain of the system according to the preset first attenuation value; and determining the preset first attenuation value as a determined oscillation attenuation value in response to the oscillation determination number being larger than or equal to a preset threshold.